greatshuyi

greatshuyi's Stars

• IObundle/iob-versat

  Coarse Grained Reconfigurable Array

  Language:C++1412

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog980245

• SeanZarzycki/openSPARC-FPU

  ASIC Design of the openSPARC Floating Point Unit

  Language:Verilog133

• thomasrussellmurphy/istyle-verilog-formatter

  Open source implementation of a Verilog formatter

  Language:C++17344

• agalimberti/NoCRouter

  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni

  Language:SystemVerilog9536

• taichi-ishitani/tnoc

  Network on Chip Implementation written in SytemVerilog

  Language:SystemVerilog14242

• google/bottlerocket

  Language:Scala10625

• anan-cn/Open-Source-Network-on-Chip-Router-RTL

  Language:Verilog6032

• gift-surg/NiftyMIC

  NiftyMIC is a research-focused toolkit for motion correction and volumetric image reconstruction of 2D ultra-fast MRI.

  Language:Python13130

• jomonkjoy/PCIe-Controller

  PCI Express ® Base Specification Revision 3.0

  Language:SystemVerilog54

• afborchert/pointer-chasing

  Utilities to measure read access times of caches, memory, and hardware prefetches for simple and fused operations

  Language:C++7216

• Project-Bonfire/Bonfire

  A implementation of a NoC router with credit based flow control

  Language:VHDL73

• firesim/firechip

  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

  Language:C5731

• shantanu5092/Bidding-arbiter

  Designed a bidding arbiter for granting bus access to the selected master

  Language:SystemVerilog1

• satputeaditya/Bidding-logic-arbiter

  Bidding logic arbiter for fairness of Bandwidth allocation

  Language:Verilog1

• danlomeli/axi-stream-arbiter

  Language:Verilog41

• nguyenquanicd/AllArbiterRTLCode

  RTL code of some arbitration algorithm

  Language:Verilog93

• enjoy-digital/litepcie

  Small footprint and configurable PCIe core

  Language:Python449110

• alexforencich/verilog-pcie

  Verilog PCI express components

  Language:Verilog1k273

• theseus-cores/theseus-cores

  Open source FPGA cores for digital signal processing (push mirror from gitlab.com/theseus-cores/theseus-cores)

  Language:Verilog135

• SI-RISCV/e200_opensource

  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

  Language:Verilog2.6k996

• NetFPGA/NetFPGA-public

  NetFPGA public repository

  173128

• mwickert/scikit-dsp-comm

  A collection of functions and classes to support signal processing and communications theory teaching and research

  Language:Python18253

• alexforencich/verilog-axi

  Verilog AXI components for FPGA implementation

  Language:Verilog1.4k417

• AmeerAbdelhadi/2D-Binary-Content-Addressable-Memory-BCAM

  Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)

  Language:Verilog178

• pheaver/netlist-verilog

  Netlist and Verilog Haskell Package

  Language:Haskell1812

• AmeerAbdelhadi/Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM

  Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)

  Language:Verilog2012

• NetFPGA/netfpga

  NetFPGA 1G infrastructure and gateware

  Language:Verilog362145

• chipmuenk/pyfda

  Python Filter Design Analysis Tool

  Language:Python63494

• corundum/corundum

  Open source FPGA-based NIC and platform for in-network compute

  Language:Verilog1.5k386