/vespa

VESPA prototyping framework for FPGA-based, accelerator-oriented SoCs

Primary LanguageCOtherNOASSERTION

VESPA is an open-source system-on-chip (SoC) prototyping platform. It is based on a 2D-mesh network-on-chip (NoC). There are four types of tiles: CPU, MEM, IO, and ACC. To use this tool, take a look to the TUTORIAL.md file in the main repository folder.

For more details, please see our ICCD'24 paper:

@misc{Montanaro_2024ICCD,
      title={A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS}, 
      author={Gabriele Montanaro and Andrea Galimberti and Davide Zoni},
      year={2024},
      eprint={2411.15574},
      archivePrefix={arXiv},
      primaryClass={cs.AR},
      url={https://arxiv.org/abs/2411.15574}, 
}

Repository organization

Here is a brief description of the main directories in the repository, please refer to the READMEs inside each of them for more information.

  • accelerators contains multiple accelerator design and integration flows, as well as many example accelerators.

  • constraints contains the constraints and attributes for each supported FPGA board (or ASIC technology).

  • socs contains the working folders for launching all Make targets. There is one working folder for each supported FPGA board (or ASIC technology).

  • rtl contains the whole RTL code base, excluding the accelerators RTL and the RTL generated in the working folder by the SoCGen and SocketGen tools.

  • soft contains bootloader, Linux kernel and root file system, and bare-metal library for each of the available processor cores. It also contains bare-metal, user space and kernel space libraries for invoking and managing accelerators.

  • tech is the destination of the RTL generated by the HLS-based and Chisel-based accelerator design flows. It is also the destination of the RTL generated with HLS for the SystemC implementation of the cache hierarchy. The generated RTL is organized based on the target FPGA (or ASIC) technology.

  • tools contains tools for design automation and for communicating with an VESPA SoC from a host machine.

  • utils contains various scripts and utilities, including the main Makefiles, the RTL file lists, and the software toolchains installation scripts.

  • .cache caches some compiled libraries so they only need to be compiled once (e.g. Xilinx simulation libraries).