helai22's Stars
T-Platz/LZSS-VHDL
An implementation of the LZSS lossless data compression algorithm in VHDL
marph91/pico-png
PNG encoder, implemented in VHDL
Aperture-Electronic/Realtime-Bicubic-16X-SuperResolution-IP
APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS
fabriziotappero/ip-cores
A huge collection of VHDL/Verilog open-source IP cores scraped from the web
hypernyan/eth_vlg
briansune/FPGA-Camera-MIPI-DVP-Verilog
FPGA Camera Parallel & MIPI Verilog
VideoGPU/MIPI_CSI2_TX
VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes
SDsupun/ipcore
40G Ethernet Stack, Final Year Project, BSc. Engineering, Department of Electronics and Telecommunication, University of Moratuwa, Sri Lanka, 2018
lewiz-support/LMAC_CORE3
Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
NVi5/Interlaken_Genesys_2
fpgasystems/Vitis_with_100Gbps_TCP-IP
100 Gbps TCP/IP stack for Vitis shells
zhujingyang520/CM0XilinxBasys3DesignKit
gatecat/h265-encoder-rtl
gatecat/CSI2Rx
Open Source 4k CSI-2 Rx core for Xilinx FPGAs
ucb-bar/fpga-zynq
Support for Rocket Chip on Zynq FPGAs
BigPig-Bro/Gowin
【例程】国产高云FPGA 开发板及其工程
FeldmeierMichael/MIPI_CSI_2
bxinquan/zynq_cam_isp_demo
基于verilog实现了ISP图像处理IP
bxinquan/zynqmp_cam_isp_demo
ISP-Lite, VIP, MIPI-RX IP实现,测试平台为KV260+AR1335 3MP@30fps
antmicro/nvme-verilog-pcie
FDU-ME-ARC/NVMeCHA
kdurant/sata_controller
try write sata controller
wove2006/sata_controller
CospanDesign/nysa-sata
CoreyChen922/sata_2_host_controller
Sata 2 Host Controller for FPGA implementation
wove2006/sata3_host_controller
EEVengers/ThunderScope
ThunderScope GitHub Repo
briansune/Tang-Nano-4K-OV2640-Color-Verilog
Tang Nano 4K OV2640 Color Verilog
darwinbeing/NetFPGA-10G-VC709
NetFPGA-10G VC709 project
marknsikora/G4_stereoscopic_depth
Project for a Nexys 4 DDR board to do stereoscopic depth detection using two ov7670 cameras