The purpose of this lab was to design a 3 bit full adder using two's compliment.
The design was made using Xylinx software along with PlanAhead and implemented on a BASYS2 FPGA Board
Files available are:
- Pdf report that contains all of the below along with procedure
- Module to show architectural behavior or full adder (FA)
- PlanAhead Generated Physical constraints
- Test bench code to test a few sample example
- Main binary file(.bit) that is then flashed onto board for Demo
- Pictures of the main schematic and waveforms
Note that all labs are required to have an example test bench and waveforms to display theoretical sucess along with a demo to demonstrate actaul success