Pinned Repositories
2D-Binary-Content-Addressable-Memory-BCAM
Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)
3D-CAE
3d-convolutional-network
ASIC-Design
Digital signal processing that can minimize the bit-rate without degradation in the signal quality is highly desirable. In telecommunication, speech compression is one of the main application where low bit rate is desired to reduce the bandwidth requirement. As per Recommendation G.711: Pulse Code Modulation (PCM) of voice frequencies by International Telecommunication Union (ITU), the standard PCM signal bit rate is 64kbits/s. This project was developed based on, Recommendation G.726: 40, 32, 24, 16kbit/s Adaptive Differential Pulse Code Modulation (ADPCM) was used to achieve low bit rates for different application requirements. The design was targeted for processing 8 independent channels in a 125 microsecond frame. In order to achieve considerable reduction in system size and instantaneous power, the FMULT/ACCUM module in ADPCM algorithm was implemented as bit serial arithmetic operations with independent floating point multiplier and accumulator. A hierarchical bottom-up design and verification approach was followed resulting in gate level synthesis of MCAC, targeted to TSMC 0.18ยตm Process technology.
cml-cgra
ASU CGRA
combinational-bnn
System Verilog code describing a fully combinational binarized neural network.
DNN_NeuroSim_V1.0
MAESTRO
An analytical cost model of DNN Dataflows (http://synergy.ece.gatech.edu/tools/maestro/)
MLP_NeuroSim_V3.0
verilog
hoangt's Repositories
hoangt/DNN_NeuroSim_V1.0
hoangt/MAESTRO
An analytical cost model of DNN Dataflows (http://synergy.ece.gatech.edu/tools/maestro/)
hoangt/MLP_NeuroSim_V3.0
hoangt/caffeine
A high performance caching library for Java 8
hoangt/CHaiDNN
HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs
hoangt/chipyard
hoangt/COMBA
A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications
hoangt/gem5
hoangt/gem5-ramulator
newest gem5 patched with Ramulator
hoangt/hwacha-net
hoangt/hwacha-template
Template for projects using the Hwacha data-parallel accelerator
hoangt/ICLR2019-OpenReviewData
Script that crawls meta data from ICLR OpenReview webpage. Tutorials on installing and using Selenium and ChromeDriver on Ubuntu.
hoangt/labeled-RISC-V
hoangt/LMAC_CORE3
Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
hoangt/machine-learning-yearning
Machine Learning Yearning book by ๐ ฐ๏ธ๐ท๐ญ๐ป๐ฎ๐ ๐
hoangt/models
Models and examples built with TensorFlow
hoangt/mysql-plnvm
Partitioned Logging in NVM implementation in InnoDB/MySQL
hoangt/mysql-with-nvdimm
To optimize the performance, InnoDB redo log buffer was ported in NVDIMM
hoangt/PAAS_V1.0
PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
hoangt/pmwcas
pmwcas
hoangt/pwc
Papers with code. Sorted by stars. Updated weekly.
hoangt/QNNPACK
Quantized Neural Network PACKage - mobile-optimized implementation of quantized neural network operators
hoangt/rc-fpga-zcu
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
hoangt/RISC-V-TLM
RISC-V SystemC-TLM simulator
hoangt/riscv-vp
RISC-V Virtual Prototype
hoangt/riscy-OOO
RiscyOO: RISC-V Out-of-Order Processor
hoangt/SCALE-Sim
hoangt/sparse-evolutionary-artificial-neural-networks
sparse neural networks before training, sparse evolutionary artificial neural networks, scalable deep learning, very high dimensional data, complex networks
hoangt/sparse-winograd-cnn
Efficient Sparse-Winograd Convolutional Neural Networks
hoangt/tensorly-notebooks
Tensor methods in Python with TensorLy