Pinned Repositories
2D-Binary-Content-Addressable-Memory-BCAM
Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)
3D-CAE
ASIC-Design
Digital signal processing that can minimize the bit-rate without degradation in the signal quality is highly desirable. In telecommunication, speech compression is one of the main application where low bit rate is desired to reduce the bandwidth requirement. As per Recommendation G.711: Pulse Code Modulation (PCM) of voice frequencies by International Telecommunication Union (ITU), the standard PCM signal bit rate is 64kbits/s. This project was developed based on, Recommendation G.726: 40, 32, 24, 16kbit/s Adaptive Differential Pulse Code Modulation (ADPCM) was used to achieve low bit rates for different application requirements. The design was targeted for processing 8 independent channels in a 125 microsecond frame. In order to achieve considerable reduction in system size and instantaneous power, the FMULT/ACCUM module in ADPCM algorithm was implemented as bit serial arithmetic operations with independent floating point multiplier and accumulator. A hierarchical bottom-up design and verification approach was followed resulting in gate level synthesis of MCAC, targeted to TSMC 0.18µm Process technology.
cml-cgra
ASU CGRA
combinational-bnn
System Verilog code describing a fully combinational binarized neural network.
DNN_NeuroSim_V1.0
MAESTRO
An analytical cost model of DNN Dataflows (http://synergy.ece.gatech.edu/tools/maestro/)
MLP_NeuroSim_V3.0
Pyverilog-1
Python-based Hardware Design Processing Toolkit for Verilog HDL
verilog
hoangt's Repositories
hoangt/combinational-bnn
System Verilog code describing a fully combinational binarized neural network.
hoangt/ActivationFunctionDemo
The "Activation Function Demo" is a demo for implementing activation function with the mathod propsed in paper: Design Space Exploration of Neural Network Activation Function Circuits
hoangt/aff3ct
A fast simulator and a library dedicated to the channel coding.
hoangt/bismo
BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
hoangt/bitfusion
Simulator for BitFusion
hoangt/bottlerocket
hoangt/caffe
Caffe: a fast open framework for deep learning.
hoangt/caffe-1
This fork of BVLC/Caffe is dedicated to improving performance of this deep learning framework when running on CPU, in particular Intel® Xeon processors (HSW+) and Intel® Xeon Phi processors
hoangt/DataStructuresAndAlgorithmsMadeEasy
Data Structures And Algorithms Made Easy
hoangt/deep-learning-coursera
Deep Learning Specialization by Andrew Ng on Coursera.
hoangt/DesignCNNAccelerators
Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
hoangt/DRAMSim2
Update: we've moved our code to a new place! This fork is to maintain page references. New repo:
hoangt/e200_opensource
The Ultra-Low Power RISC Core
hoangt/FAST
Framework for Heterogeneous Medical Image Computing and Visualization
hoangt/gem5_arm_fullsystem_files_generator
Generator of kernels, bootloaders, DTBs and disk images for aarch32 and aarch64 gem5 Full System simulations (updated April 2018)
hoangt/gltracesim
A graphics tracing and replay framework to explore system-level effects on heterogeneous CPU+GPU memory systems.
hoangt/Highlight-Research-Articles
A curated list of the most cited machine learning / deep learning articles, papers, blogs, ..
hoangt/lut_ldpc
LUT LDPC is a collection of software tools to design and test LDPC decoders based on discrete message passing decoding using lookup tables
hoangt/lut_ldpc_vhdl
VHDL Code generation for LUT-based LDPC decoders exported from LUT-LDPC
hoangt/MLP_NeuroSim_V2.0
hoangt/mlpack
mlpack: a scalable C++ machine learning library --
hoangt/reflex
ReFlex: Remote Flash == Local Flash
hoangt/reloc
Designing Relocatable FPGA Partitions with Vivado Design Suite
hoangt/ReonV
ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.
hoangt/rocket-chip
Rocket Chip Generator
hoangt/Speckle
A wrapper for the SPEC CPU2006 benchmark suite.
hoangt/T13x
An Extended Version of the T0x multithreaded cores, with custom dsp instructions, and parallel excecution. The core is pin-to-pin compatible with the pulpino riscy cores
hoangt/tensorflow
Computation using data flow graphs for scalable machine learning
hoangt/tf_compress
General library for compressing tensorflow models
hoangt/zynq-template
Template design and boot image for ZYNQ and ZYNQ Ultrascale+ Development Boards