Pinned Repositories
Algorithms
Sorting, Search Algorithms' Implementations with Cpp, Python
ARM-Pipelined-Processor-With-Branch-Predictor
A 32-bit ARM Pipelined Processor Implementation in Verilog HDL along with Forwarding, Hazard Detection, Handling and a Branch Predictor.
ARM-Processor-Designs
Repository with single-cycle, multi-cycle, and pipelined processor designs for architecture labs. Enables study and experimentation to understand processor functionality and performance improvements through different designs.
Light-Based-LED-Driver
TSL 2561 light sensor based LED and LCD 5110 driver implementations with Tiva TM4C123 board.
Maze-Hanoi-Determinant-Calc-BST-HT
Implemented Solvers for Hanoi and Maze Games, Alongside a Determinant Calculator that utilizes from Binary Search Tree (BST) and Hash Table (HT).
Quality-of-Service-Based-Queuing
To optimize QoS, a queuing algorithm was implemented using Verilog HDL on FPGAs for networks.
SerialX-UART500
Explore our VHDL implementations of UART Receiver and Transmitter modules for FPGA-based systems. These modules ensure high reliability and accuracy in serial communication, featuring configurable clock frequencies and baud rates. Perfect for FPGA developers.
Socket-Proxy-Server
This project implements a simple system with three nodes: Client, Proxy, and Server. The Server holds a list of 10 elements, and the Proxy maintains a cached version of the Server's table. The Client communicates with the Proxy, which interacts with the Server when necessary. Nodes exchange messages using a specific format.
Swiss-Stopwatch
Project is a high-precision chronometer using VHDL, intended for implementation on an FPGA. The chronometer is designed to operate with nanosecond (ns) precision and is capable of accurately measuring elapsed time in milliseconds, seconds, and minutes. The design has been tested using a VHDL test bench and verified with the XSim extensively.
Virtual-Machine
Implementation of an LC3 Virtual Machine with a Simple Operating System (OS) that Executes Assembly Language Programs.
htmos6's Repositories
htmos6/Quality-of-Service-Based-Queuing
To optimize QoS, a queuing algorithm was implemented using Verilog HDL on FPGAs for networks.
htmos6/Socket-Proxy-Server
This project implements a simple system with three nodes: Client, Proxy, and Server. The Server holds a list of 10 elements, and the Proxy maintains a cached version of the Server's table. The Client communicates with the Proxy, which interacts with the Server when necessary. Nodes exchange messages using a specific format.
htmos6/Algorithms
Sorting, Search Algorithms' Implementations with Cpp, Python
htmos6/ARM-Pipelined-Processor-With-Branch-Predictor
A 32-bit ARM Pipelined Processor Implementation in Verilog HDL along with Forwarding, Hazard Detection, Handling and a Branch Predictor.
htmos6/ARM-Processor-Designs
Repository with single-cycle, multi-cycle, and pipelined processor designs for architecture labs. Enables study and experimentation to understand processor functionality and performance improvements through different designs.
htmos6/Autonomous-Master-Robot-GUI
KT-007-GUI is a graphical user interface application developed using the C++ Qt framework. The application is designed to facilitate the drawing of paths and adjustment of speeds for mobile robots. Additionally, the route planner provides an opportunity for real-time route tracking, enabling the user to to detect any anomalies in the master robot's
htmos6/Data-Structures
This repository is a great resource for anyone looking to learn about or implement data structures in C++ as it provides implementations of various data structures in C++.
htmos6/EE374-Final-Project
EE374 final project. High Voltage Line Parameters' Calculations.
htmos6/free-programming-books
:books: Freely available programming books
htmos6/Hacker-Rank-Solutions
This repo contains C++ solutions to problems from HackerRank. The problems are algorithmic and require C++ to solve. The solutions may be useful for improving problem-solving skills in C++.
htmos6/Image-Video-Processing-and-AI
OpenCV training course materials for open source purposes. Includes exercises solved my Mehmet.
htmos6/Light-Based-LED-Driver
TSL 2561 light sensor based LED and LCD 5110 driver implementations with Tiva TM4C123 board.
htmos6/Maze-Hanoi-Determinant-Calc-BST-HT
Implemented Solvers for Hanoi and Maze Games, Alongside a Determinant Calculator that utilizes from Binary Search Tree (BST) and Hash Table (HT).
htmos6/SerialX-UART500
Explore our VHDL implementations of UART Receiver and Transmitter modules for FPGA-based systems. These modules ensure high reliability and accuracy in serial communication, featuring configurable clock frequencies and baud rates. Perfect for FPGA developers.
htmos6/Swiss-Stopwatch
Project is a high-precision chronometer using VHDL, intended for implementation on an FPGA. The chronometer is designed to operate with nanosecond (ns) precision and is capable of accurately measuring elapsed time in milliseconds, seconds, and minutes. The design has been tested using a VHDL test bench and verified with the XSim extensively.
htmos6/Tiva-TM4C123GH6PM-Microprocessor-Projects
This repo contains projects exploring Tiva TM4C123GH6PM microprocessor. It covers stacks, subroutines, general programming, and specific features like Parallel I/O, SysTick Timer, Timer and ADC. These projects aim to give a comprehensive understanding of the microprocessor and serve as a starting point for further development. Explore and discover.
htmos6/Virtual-Machine
Implementation of an LC3 Virtual Machine with a Simple Operating System (OS) that Executes Assembly Language Programs.
htmos6/WebSocket-Performance-Profiler-FastAPI-vs-Tornado
Benchmarking Performance of WebSocket frameworks of FastAPI and Tornado in Python, Enhanced by Matplotlib Visualization. Ideal for High-Frequency Trading (HFT) Applications.
htmos6/Autonomous-Master-Robot-Swarm-Systems
The repository contains code and configurations for a mobile robot control system. It's optimized for robust navigation, including path planning, speed control, and anomaly detection. Features such as TCP/IP communication, encoder and IMU calibration, motor driver control, odometry, and speed estimation ensure precise and efficient operation.
htmos6/Flex-PWM500
The PWM (Pulse Width Modulation) Generator creates a PWM signal to control PWM-driven devices. It allows configurable clock and PWM frequencies via generics. The duty cycle, input as a 7-bit signal, adjusts the proportion of time the signal is high.
htmos6/HDL-Bits-Solutions
HDL bit website solutions for Verilog practices
htmos6/Mario-Reinforcement-Learning
htmos6/Metu-Course-Capacity-Checker
In order to check course capacities automatically, I have designed course capacity questioning bot by selenium. If course capacity is available, it warns us by playing warning sound.
htmos6/RAM
htmos6/Redis
C++ project implementing Winsock2 for TCP communication with a Redis server. Facilitates data exchange and storage between connected clients and Redis.
htmos6/Selenium-Twitter-Automation
Automatic like bot for Twitter. Searches hashtag and writes their tweets to a .txt file.
htmos6/Verilog-System-Design-Questions
htmos6/VHDL-Component-Library
The repository is a VHDL component library that includes all necessary digital components and basic building blocks for digital circuits. (Under Development))
htmos6/VHDL-Ref
htmos6/WireShark-and-HTTP
This GitHub repository demonstrates implementing a simple HTTP client in Python to interact with a Flask server. The server runs a D'Hondt-style election simulator with region and seat information for an example-country election. It provides APIs for adding/deleting parties and running the D'Hondt simulation with party votes provided by the client.