htmos6/ARM-Processor-Designs

Repository with single-cycle, multi-cycle, and pipelined processor designs for architecture labs. Enables study and experimentation to understand processor functionality and performance improvements through different designs.

Computer-Architecture-Verilog

This repository contains Verilog implementations for various building blocks that are used in computer architecture, such as the Arithmetic Logic Unit (ALU), shifters, generators, memory, multiplexers, registers, and more.

Verilog Building Blocks for Computer Architecture

ALU.v : Verilog implementation for Arithmetic Logic Unit (ALU)
combinational_shifter.v : Verilog implementation for combinational shifter
constant_value_generator.v : Verilog implementation for constant value generator
controller.v : Verilog implementation for controller
data_path_v.v : Verilog implementation for data path
decoder2to4.v : Verilog implementation for 2-to-4 decoder
decoder4to16.v : Verilog implementation for 4-to-16 decoder
hexto7seg.v : Verilog implementation for hexadecimal to 7-segment decoder
memory.v : Verilog implementation for memory
multiplexer16to1.v : Verilog implementation for 16-to-1 multiplexer
multiplexer2to1.v : Verilog implementation for 2-to-1 multiplexer
multiplexer4to1.v : Verilog implementation for 4-to-1 multiplexer
register_file.v : Verilog implementation for register file
register_synchronous_reset.v : Verilog implementation for register with synchronous reset
register_synchronous_reset_write_en.v : Verilog implementation for register with synchronous reset and write enable