infini8-13

Accelerating_Standard_and_Modified_AES128

courseraforums

[Implementation Updated] Anonymized versions of the discussion threads from the forums of 60 Coursera MOOCs

des-aes-128bit-verilog

hdlbits-verilog-funda

low-power-3tnand

MaskRCNN_tryout

Instance Segmentation using Mask RCNN(with pretrained weights of COCO dataset)

Morse-Decoder-Schematic

Morse Code Decoder using Digital Logic

riscv-ms-soc

A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier

riscv-tlv-core

A simple implementation of a RISC-V core (RV32I) written in TL Verilog.

SHA256_HW_Accelerator

infini8-13/powerline-fault-detection

infini8-13/Accelerating_Standard_and_Modified_AES128

infini8-13/SHA256_HW_Accelerator

infini8-13/aes-128-tlverilog

Implementation of AES-128 bit key algorithm in TL-Verilog

infini8-13/benchmarks

EPFL logic synthesis benchmarks

infini8-13/convolutional_autoencoder

Autoencoder constructed with CNN in Keras for Image Denoising

infini8-13/cops_algorithms

Repository for algorithms contributed in CSOC

infini8-13/CSrankings

A web app for ranking computer science departments according to their research output in selective venues, and for finding active faculty across a wide range of areas.

infini8-13/doc_scanner

infini8-13/dog_Vs_cat-cnn

A simple CNN for classifying dogs and cats with a small dataset, accompanied by data augmentation and VGG-16

infini8-13/edXBuildingARISCVCPUCore

edX LinuxFoundationX LFD111x Building a RISC-V CPU Core

infini8-13/eFPGA---RTL-to-GDS-with-SKY130

This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk

infini8-13/fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

infini8-13/Hacker-Introduction

infini8-13/Language-Classifier-with-naive-bayes-model

Classification of sentences into different languages using Naive Bayes probabilistic approach, trained with sentences of 3 languages[Slovak, Czech & English]

infini8-13/learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

infini8-13/learnopencv

Learn OpenCV : C++ and Python Examples

infini8-13/Magic-Square-With-Birth-Date

Generates a magic matrix,with the input of birthdate, in the format of DD MM YYYY.

infini8-13/many-passwords

Default password for each devices. 🐱‍💻 Leave a star if you like this project! ⭐️

infini8-13/nlp_coursera

infini8-13/openpiton

The OpenPiton Platform

infini8-13/serv

SERV - The SErial RISC-V CPU

infini8-13/smartcrop.py

smartcrop implementation in Python

infini8-13/SOFA

SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA

infini8-13/strava-club-leaderboard

infini8-13/timelapse_cv2

infini8-13/Understanding-GANs

Intro to Generative Adversarial Networks with MNIST digits dataset [DCGAN]

infini8-13/verilog-onestop

Collection of verilog labs starting from the basics to a good level of sequential logic implementation

infini8-13/vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

infini8-13/YT_dwnloader-cli

Download audio stream,video stream, or video along with audio just thru command line