intel/systemc-compiler

Multiple assignments in C

mzau opened this issue · 2 comments

mzau commented

I'm not shure if mupltiple assignemnts in system verilog are defined, as:

  A = B = 5;

but ICSC compiles a C multiple assigment one to one into the system verilog output. If thats allowed in SV, at least Intel's Quartus 18.1 will not accept this.
Changing to

  A = 5;
  B = 5;

at the other hand is ok.

mikhailmoiseev commented

Thank you for this issue. It has been fixed. Will commit the updated version near days.