Is there any intermediate code similar to AST generation during conversion to SystemVerilog
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The ICSC User Guide says “SystemVerilog code generation is done with svc_target function.” I want to know how the transformation is realized and whether there is an intermediate part between the two language.
The transformation is described in: https://github.com/intel/systemc-compiler/blob/main/doc/papers/icsc.pdf
There are multiple IRs used in the tool: Clang CFG/AST, results of constant propagation analysis and statements properties prepared to generate SV code. If you have any specific questions, will try to help you.
I read icsc.pdf, but I found that it says convert to Verilog instead of SystemVerilog , is there a command to switch the output file type? Then, can I directly output or generate a file with clang AST information in icsc？
There is only one output format which is SystemVerilog, please consider Verilog or SV as short form of it.
ICSC does not generate SystemC process AST, but it is easy to implement that in ScTraverseConst::run(), see stmtInfo.run(funcDecl, 0); as an example.
Sorry, I still don't know how to operate SystemC Process AST, could you give me more specific guidance? For example, I want to generate AST of dut.h in examples/counter, what should I do? I am also interested in the Systemc-to-Verilog Compiler (SVC). I think it may be a historical version of ICSC. Is there any way I can download it？
SystemC process is C++ function, so to get AST for a process it needs: 1) find the process function declaration, 2) parse AST directly or with clang::RecursiveASTVisitor. ICSC finds process function declarations, but it is not difficult to do that from SC_THREAD/SC_METHOD macros.
There is no reason to get old version of ICSC as the current is the best, but you can use previous git commits.
Thanks for the guidance. I think I know what to do. ICSC is a great program, and if I have any questions about it, I will keep asking you here. Thanks for your patient reply.