This tutorial is an academic related experimental base and explores the various views that make-up a digital design flow using standard-cell library. It illustrates how to use a set of EDA Tools like Synopsys and Cadence ASIC Design tools to map RTL designs down to these standard cells and ultimately silicon.
The tutorial will discuss the key tools used for synthesis, simulation, verifying testing scenarios and power as well as timing analysis as a sign off metric. This tutorial requires entering commands manually for each of the tools to enable students to gain a better understanding of the detailed steps involved in this process.
Using various Electronics Design Autmation tools like, Synopsys Design Compiler for Synthesis, Cadence Innovus for Place-and-Route, Synopsys PrimeTime for Power Analysis, and various other tools for testing and verifying Verilog RTL Models
VLSI-Laboratory-NIT-Rourkela
Laboraory manuals and Discussion - The laboratory activities reflects the work being conducted as an academic course work for post graduate students at NIT Rourkela India towards completion of graded work as assignment in a semester. The following hierarchy may be pursued (not mandatory) to understand part of the steps involved in the RTL to GDSII Integrated Circuit (digital) design semi-custom flow.
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RTL Simulation- Synopsis_Synthesis_Simulation.pdf (Synopsis VCS and Design Vision) -
RTL Simulation- ManualExp1.pdf (Cadence NCVerilog) -
Linting - LintingManual.pdf (Cadence irun, NCLaunch) -
Code Coverage - CodeCoverage.pdf (Cadence IMC, NCVerilog) -
Synthesis - Synthesis-I.pdf (Cadence Genus without Constraint) Synthesis-II.pdf (Cadence Genus with Constraint) -
Logic Equivalence- Logic_Equivalence.pdf (Cadence LEC) -
ATPG- ATPG-I.pdf (Synopsys TetraMax for combinational design) ATPG-II.pdf (Synopsys TetraMax for Scan Chain insertion in Sequential Design) -
Power Analysis - PowerAnalysis.pdf (Synopsys VCS and Design Vision) -
STA- StaticTimingAnalysis.pdf (Cadence Tempus)
Further work on Signoff (two types of sign-off's: front-end sign-off and back-end sign-off) is on progress and will be updated soon. This tutorial is a work in progress, and needs updation frequently to be in compliance with the ongoing demands.
Acknowledgement
The author, JPM, would like to thank SMDP-C2SD, sponsored project MEITY, Government of India.
He would also like to thank the knowledge support from earlier courses at ECE department of NIT Rourkela through various courseworks.
The views and conclusions contained herein are those of the author and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of neither the institute nor the Indian Government.