jsburke's Stars
pomber/git-history
Quickly browse the history of a file from any git repository
riscv-boom/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
BleuBleu/FamiStudio
FamiStudio NES Music Editor
freechipsproject/chisel-bootcamp
Generator Bootcamp Material: Learn Chisel the Right Way
taylorconor/quinesnake
A quine that plays snake over its own source!
B-Lang-org/bsc
Bluespec Compiler (BSC)
ucb-bar/chisel-tutorial
chisel tutorial exercises and answers
fabianschuiki/llhd
Low Level Hardware Description — A foundation for building hardware design tools.
bluespec/Flute
RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
bluespec/Piccolo
RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
stevehoover/warp-v
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
csail-csg/riscy-OOO
RiscyOO: RISC-V Out-of-Order Processor
michaeljclark/riscv-probe
Simple machine mode program to probe RISC-V control and status registers
google/bottlerocket
CTSRD-CHERI/bluecheck
A generic test bench written in Bluespec
RischardV/riscv-alphanumeric-shellcoding
Alphanumeric+1 shellcoding tools for RISC-V
FPSG-UIUC/augury
Using Data Memory-Dependent Prefetchers to Leak Data at Rest
reverseame/processfuzzyhash
Volatility plugin to calculate and compare Windows processes fuzzy hashes
PhoenixRite/catholicism-submission-tracker
Code for bot that reads /r/Catholicism/new and determines how many times per week a user posts.