katieworton

katieworton's Stars

• EPCCed/cirrus-docs

  539

• ARCHER2-HPC/archer2-docs

  Repository for ARCHER2 documentation

  1843

• Linaro/jipdate

  Linaro JIRA Update Tool

  Language:Python622

• codecrafters-io/build-your-own-x

  Master programming by recreating your favorite technologies from scratch.

  Language:Markdown324k30k

• Fmstrat/wintile

  Windows 10 window tiling for GNOME

  Language:JavaScript43652

• lukeg101/lplzoo

  Fine-grain implementations of common lambda calculi in Haskell, tested with QuickCheck

  Language:Haskell361

• gcc-mirror/gcc

  Language:C++9.5k4.4k

• TheThirdOne/rars

  RARS -- RISC-V Assembler and Runtime Simulator

  Language:Java1.2k241

• andrescv/jupiter

  RISC-V Assembler and Runtime Simulator

  Language:JavaScript42537

• mortbopet/Ripes

  A graphical processor simulator and assembly editor for the RISC-V ISA

  Language:C++2.7k278

• TUM-LRR/era-gp-sim

  ERA-Großpraktikum Simulatorentwicklung

  Language:C++164

• openhwgroup/cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  Language:Assembly2.3k706

• microsoft/calculator

  Windows Calculator: A simple yet powerful calculator that ships with Windows

  Language:C++30k5.5k

• heydtn/mips-pipeline

  MIPS Processor pipeline written in verilog

  Language:Verilog2

• fossi-foundation/fossi-foundation.github.io

  FOSSi Foundation Website

  Language:HTML1745

• chao-peng/ST_Coursework1819

  Language:Java512

• Digilent/vivado-boards

  Language:Tcl406215

• wd5gnr/icestickPWM

  Simple USB to PWM Peripheral using Lattice iCEStick (Hackaday demo)

  Language:Verilog234

• westerndigitalcorporation/swerv_eh1

  A directory of Western Digital’s RISC-V SweRV Cores

  Language:SystemVerilog858132

• mhyousefi/MIPS-pipeline-processor

  A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

  Language:Verilog15133

• toggl/toggl_api_docs

  Documentation for the Toggl API

  1.4k235

• xenia-project/xenia

  Xbox 360 Emulator Research Project

  Language:C++8.4k1.2k

• riscvarchive/riscv-binutils-gdb

  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.

  Language:C149234

• microsoft/MS-DOS

  The original sources of MS-DOS 1.25, 2.0, and 4.0 for reference purposes

  Language:Assembly30.9k4.4k

• riscvarchive/riscv-wiki

  25039

• xoreaxeaxeax/sandsifter

  The x86 processor fuzzer

  Language:Python4.9k351

• JabRef/jabref

  Graphical Java application for managing BibTeX and biblatex (.bib) databases

  Language:Java3.7k2.6k

• darklife/darkriscv

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  Language:Verilog2.2k292

• karan/Projects

  :page_with_curl: A list of practical projects that anyone can solve in any programming language.

  45.6k10.6k

• karan/Projects-Solutions

  :pager: Links to others' solutions to Projects (https://github.com/karan/Projects/)

  4.2k1.3k