kbrunham-intel

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

fpga-partial-reconfig

Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow

pfr-wilson-city

design-flows

Quartus Prime Pro Design Flows

linguist

Language Savant. If your repository's language is being reported incorrectly, send us a pull request!

personal.kbrunham.linux.i3c-test

Linux kernel source tree for testing I3C

remake

Enhanced GNU Make - tracing, error reporting, debugging, profiling and more

u-boot

"Das U-Boot" Source Tree

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

u-boot

"Das U-Boot" Source Tree

kbrunham-intel/design-flows

Quartus Prime Pro Design Flows

kbrunham-intel/linguist

Language Savant. If your repository's language is being reported incorrectly, send us a pull request!

kbrunham-intel/personal.kbrunham.linux.i3c-test

Linux kernel source tree for testing I3C

kbrunham-intel/remake

Enhanced GNU Make - tracing, error reporting, debugging, profiling and more

kbrunham-intel/verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server