Generating complete schematic out of VHDL files

Question

Generating complete schematic out of VHDL files

Opened this issue 6 years ago · 2 comments

Hello, do you think one day symbolator could be used to parse one or more VHDL files to generate a schematic of the instanced components/wires?

Answer 1 · 2021-04-09T20:06:23.000Z

You may be looking to use something like netlistsvg. I wrote a blog post on how to generate blog diagrams from VHDL using the open source FPGA toolchain here.

Answer 2 · 2021-04-09T21:40:30.000Z

If you are using Sphinx, you might also want to consider https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/