laurentc2

Pinned Repositories

ASAP7_for_KLayout
KLayout technology files for ASAP7 FinFET educational process
183
bsg_sv2v
A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
Language:Python2 0 00
FreePDK45_for_KLayout
KLayout technology files for FreePDK45
Language:SourcePawn18 2 010
LTspice2Kicad
LTspice to Kicad schematic conversion
Language:Python26 0 35
MOSIS_SCMOS_for_KLayout
KLayout technology files for MOSIS SCMOS generic process
21
SKY130_for_KLayout
KLayout technology files for Skywater SKY130
Language:Makefile37 7 912
Spice2Verilog
Spice netlist to Verilog netlist translation
Language:Perl51
Verilog2Spice
Simple strutured VERILOG netlist to SPICE netlist translator
Language:Python21 0 06
vhdl2verilog
Language:VHDL3 0 00
rst2pdf
Use a text editor. Make a PDF.
Language:Python538 34 818148

laurentc2's Repositories

laurentc2/SKY130_for_KLayout
KLayout technology files for Skywater SKY130
Language:Makefile37 7 912
laurentc2/LTspice2Kicad
LTspice to Kicad schematic conversion
Language:Python26 0 35
laurentc2/Verilog2Spice
Simple strutured VERILOG netlist to SPICE netlist translator
Language:Python21 0 06
laurentc2/ASAP7_for_KLayout
KLayout technology files for ASAP7 FinFET educational process
183
laurentc2/FreePDK45_for_KLayout
KLayout technology files for FreePDK45
Language:SourcePawn18 2 010
laurentc2/Spice2Verilog
Spice netlist to Verilog netlist translation
Language:Perl51
laurentc2/vhdl2verilog
Language:VHDL3 0 00
laurentc2/bsg_sv2v
A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
Language:Python2 0 00
laurentc2/MOSIS_SCMOS_for_KLayout
KLayout technology files for MOSIS SCMOS generic process
21