lexgolovchenko's Stars
veryl-lang/veryl
Veryl: A Modern Hardware Description Language
nickg/nvc
VHDL compiler and simulator
VHDL-LS/rust_hdl
jeremiah-c-leary/vhdl-style-guide
Style guide enforcement for VHDL
kevinpt/symbolator
HDL symbol generator
alexforencich/verilog-wishbone
Verilog wishbone components
SystemRDL/PeakRDL
Control and status register code generator toolchain
kward/shunit2
shUnit2 is a xUnit based unit test framework for Bourne based shell scripts.
zachjs/sv2v
SystemVerilog to Verilog conversion
bespoke-silicon-group/basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
gsmecher/pyxsi
Python/C/RTL cosimulation with Xilinx's xsim simulator
tomverbeure/ecp5_jtag
Use ECP5 JTAG port to interact with user design
fvutils/pyvsc
Python packages providing a library for Verification Stimulus and Coverage
MikePopoloski/slang
SystemVerilog compiler and language services
ggrossetie/asciidoctor-web-pdf
Convert AsciiDoc documents to PDF using web technologies
chiselverify/chiselverify
A dynamic verification library for Chisel.
accellera-official/systemc
SystemC Reference Implementation
esynr3z/pyhdlsim
Example of Python and PyTest powered workflow for a HDL simulation
pConst/basic_verilog
Must-have verilog systemverilog modules
olofk/fifo
Generic FIFO implementation with optional FWFT
wallento/wavedrompy
WaveDrom compatible python command line
olofk/fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
olofk/edalize
An abstraction library for interfacing EDA tools
dpretet/svut
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
dpretet/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
svunit/svunit
dpretet/svlogger
SystemVerilog Logger
cluelogic/cluelib
A generic class library in SystemVerilog
VUnit/vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
ZipCPU/wb2axip
Bus bridges and other odds and ends