Pinned Repositories
A-convolution-kernel-implemented-by-Vivado-HLS
This project implements a convolution kernel based on vivado HLS on zcu104
A-multi-functions-digital-clock-based-on-8051
A multi-functions digital clock based on 8051, the corresponding proteus simulation circuit is also provided.
CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
Cool-compiler
Solution to Cool compiler assignment
CS231n-solution
My solution to CS231n
EE113_PROCESSOR
The reference design of EE113's final project (Digital integrated Circuit design Fall 2020) at ShanghaiTech University
openhls
PyTorch model to RTL flow for low latency inference
Pintos-OS
Solution for Pintos assignment
RefSCAT
RefSCAT: Paper's Result and Benchmark
utopia-hls
Utopia: a High-Level Synthesis framework
lirui-shanghaitech's Repositories
lirui-shanghaitech/A-convolution-kernel-implemented-by-Vivado-HLS
This project implements a convolution kernel based on vivado HLS on zcu104
lirui-shanghaitech/EE113_PROCESSOR
The reference design of EE113's final project (Digital integrated Circuit design Fall 2020) at ShanghaiTech University
lirui-shanghaitech/Pintos-OS
Solution for Pintos assignment
lirui-shanghaitech/A-multi-functions-digital-clock-based-on-8051
A multi-functions digital clock based on 8051, the corresponding proteus simulation circuit is also provided.
lirui-shanghaitech/Cool-compiler
Solution to Cool compiler assignment
lirui-shanghaitech/CS231n-solution
My solution to CS231n
lirui-shanghaitech/auto-ncmdump
使用 ncmdump ，实现全自动网易云音乐ncm格式转mp3
lirui-shanghaitech/ctoverilog
A C to verilog compiler
lirui-shanghaitech/dynamatic
lirui-shanghaitech/ecosoc
Automatically exported from code.google.com/p/ecosoc
lirui-shanghaitech/learning-cmake
learning cmake
lirui-shanghaitech/Learning-Resource
Collections of some learning materials
lirui-shanghaitech/legup-dockerfile-1
lirui-shanghaitech/legup-tmr
lirui-shanghaitech/LegUpAsicImp
Master Thesis: High-Level synthesis for ASIC implementation using LegUp
lirui-shanghaitech/libmem
lirui-shanghaitech/Light-HLS
Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation.
lirui-shanghaitech/LLVM-9.0-Learner-Tutorial
A blog for LLVM(v9.0.0 or v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM and accomplish a complete project for FPGA High-Level Synthesis with it.
lirui-shanghaitech/patmos_HLS
Hardware Accelerators (HwAs) constructed in Vivado HLS
lirui-shanghaitech/range-analysis
Static range analysis for the LLVM compiler infrastructure.
lirui-shanghaitech/rbaa
Range Based Alias Analysis for LLVM
lirui-shanghaitech/RELISH
Runahead Execution of Load Instructions via Sliced Hardware (RELISH) -- a High level synthesis optimisation pass, which automatically constructs helper circuits used to prefetch load instructions.
lirui-shanghaitech/revsca
lirui-shanghaitech/RevSCA-2.0
lirui-shanghaitech/roccc-2.0
lirui-shanghaitech/StitchUp
StitchUp is a plugin to the LegUp High Level Synthesis tool that enables the generation of fault tolerant FPGA circuits.
lirui-shanghaitech/Syncopation
Automated adaptive clock management tool for LegUp HLS-generated circuits on FPGA.
lirui-shanghaitech/tclsh-wrapper
A tiny wrapper for Tcl/Tk's tclsh and wish
lirui-shanghaitech/wfv
IMPORTANT NOTICE: This implementation is long outdated. The new libwfv will be released soon. Whole-Function Vectorization is an algorithm that transforms a scalar function in such a way that it computes W executions of the original code in parallel using SIMD instructions (W is the target architecture's SIMD width). This implementation of the algo
lirui-shanghaitech/xronos
Xronos: High Level Synthesis of Streaming Applications