m-labs/misoc

Issues

• pip install of tag 0.12 fails

  #146 opened a year ago by shareefj
  5

• fix or remove Ultrascale SDRAM init

  #92 opened 2 years ago by sbourdeauducq
  4

• misoc@2022-04-07 fail with either latest migen built from source (2022-09-02) and with migen 0.9.2

  #131 opened 2 years ago by doronbehar
  1

• Standard 1 bit SPI mode for spi_flash not available?

  #87 opened 6 years ago by danielkucera
  2

• different clocking of differentiator and integrator

  #102 opened 4 years ago by nkrackow
  3

• Wrong version in `setup.py`

  #100 opened 5 years ago by FFY00
  0

• register_rom weirdness

  #96 opened 6 years ago by keesj
  2

• Papilio pro default rom size is too small

  #60 opened 6 years ago by FelixVi
  8

• CSRStorage with write_from_dev=True seems broken in simulation

  #95 opened 6 years ago by mithro
  3

• merge a7ddrphy and k7ddrphy

  #57 opened 7 years ago by sbourdeauducq
  5

• RGMII on Sayma broken

  #55 opened 6 years ago by jordens
  8

• Wanted to Build a small SoC

  #93 opened 6 years ago by bhatmahadev6
  1

• software not rebuilt after gateware change

  #91 opened 6 years ago by danielkucera
  0

• Binutils compilation

  #83 opened 7 years ago by danielkucera
  0

• Record.connect return value not used

  #80 opened 7 years ago by tpwrules
  3

• flterm: memory leak

  #66 opened 7 years ago by jbqubit
  7

• DDR3-related error in Vivado timing report for Ultrascale

  #75 opened 7 years ago by sbourdeauducq
  1

• spi: first half-cycle (setup period) of a chained, pure read uses the write divider instead of the read divider

  #76 opened 7 years ago by jordens
  0

• replace liteeth _preamble_crc CSR with constant

  #68 opened 7 years ago by sbourdeauducq
  0

• liteeth: rename dv to rx_dv

  #71 opened 7 years ago by sbourdeauducq
  0

• liteeth: remove dw parameterization

  #70 opened 7 years ago by sbourdeauducq
  2

• Gigabit ethernet PHY for serial links/SFP

  #54 opened 7 years ago by jordens
  2

• kasli/spi_flash: investigate and implement quad i/o read

  #74 opened 7 years ago by jordens
  0

• clean up memory regions, names, offsets

  #73 opened 7 years ago by jordens
  0

• SPI clock glitches on CS transitions

  #65 opened 7 years ago by jordens
  0

• liteeth: remove MII clock output

  #72 opened 7 years ago by sbourdeauducq
  0

• fix liteeth error counter atomicity problem

  #69 opened 7 years ago by sbourdeauducq
  2

• remove gap checker from liteeth

  #67 opened 7 years ago by sbourdeauducq
  1

• check that liteeth MAC observes minimum interframe gap

  #62 opened 7 years ago by jordens
  1

• DDR3 broken on some Sayma boards

  #63 opened 7 years ago by sbourdeauducq
  5

• Compiling gcc-7.2.0

  #61 opened 7 years ago by FelixVi
  5

• Paths broken when using Cygwin and Xilinx tools in Windows

  #59 opened 7 years ago by FelixVi
  1

• liteeth should be tolerant to truncated or garbled preambles

  #64 opened 7 years ago by jordens
  1

• remove FlipFlop

  #51 opened 7 years ago by sbourdeauducq
  0

• cross check SPI core w.r.t. Vivado changes

  #58 opened 7 years ago by jordens
  0

• support 4 byte spi flash addressing

  #53 opened 7 years ago by jordens
  1

• error: Could not find a version that satisfies the requirement asyncserial (from miso c) (from versions: )

  #52 opened 7 years ago by erickson-nist
  6

• setup.py fails on Ubuntu 16.04

  #50 opened 8 years ago by John-K
  2

• Framebuffer core depends on migen.actorlib

  #46 opened 8 years ago by mithro
  1

• Create a "spi settings" type thing (in same vein as the SDRAM settings)

  #48 opened 8 years ago by mithro
  2

• define stream behavior when stb=0 and eop=1

  #43 opened 8 years ago by sbourdeauducq
  2

• remove converter reset from liteeth mii.py

  #44 opened 8 years ago by sbourdeauducq
  0

• Wishbone SRAM: support memories larger than the bus width

  #42 opened 8 years ago by sbourdeauducq
  0

• move liteeth FullMemoryWE transform to migen.build

  #41 opened 8 years ago by sbourdeauducq
  0

• liteeth: safe detection of oversized frames

  #39 opened 8 years ago by sbourdeauducq
  3

• minicon: avoid oversized address signal

  #40 opened 8 years ago by sbourdeauducq
  0

• asyncserial dependency not documented

  #37 opened 9 years ago
  2

• BIOS should use '\r\n' line endings

  #38 opened 9 years ago by mithro
  0

• Avoid building all software packages for simple SoCs

  #36 opened 9 years ago by enjoy-digital
  1

• Usage of symlinks on Windows is not convenient

  #35 opened 9 years ago by enjoy-digital
  3