rams have problems with disconnected reads

[renau]

Describe the bug

connect \RD_DATA { \lg_8 \lg_7 }

but connected with 5 read ports
name:\ram_history depth:16 wrports:1 rdports:5

When opt -fast runs before, it is OK:
name:\ram_history depth:16 wrports:1 rdports:2

ERROR: Found error in internal cell \FetchTargetQueue.\\ram_history ($mem) at kernel/rtlil.cc:717:
  cell $mem \\ram_history
    parameter \RD_TRANSPARENT 5'11111
    parameter \WR_CLK_POLARITY 1'1
    parameter \RD_CLK_POLARITY 5'11111
    parameter \INIT 1'x
    parameter \WR_CLK_ENABLE 1'1
    parameter \RD_CLK_ENABLE 5'11111
    parameter \WIDTH 90
    parameter \MEMID "\\ram_history"
    parameter \RD_PORTS 5
    parameter \WR_PORTS 1
    parameter \ABITS 4
    parameter \OFFSET 0
    parameter \SIZE 16
    connect \RD_CLK { \clock \clock \clock \clock \clock }
    connect \WR_CLK \clock
    connect \RD_EN { \lgraph_cell_1731 \lgraph_cell_1731 \lgraph_cell_1731 \lgraph_cell_1731 \lgraph_cell_1705 }
    connect \RD_ADDR { \io_com_ftq_idx \lgraph_cell_1690 \io_get_ftq_pc_ftq_idx \lgraph_cell_1738 \lgraph_cell_130 }
    connect \RD_DATA { \lg_8 \lg_7 }
    connect \WR_EN { \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 \lgraph_cell_3844 }
    connect \WR_ADDR \lgraph_cell_988
    connect \WR_DATA \lgraph_cell_989
  end

To Reproduce

lgraph> inou.liveparse files:boom.system.TestHarness.BoomConfig.orig.v

lgraph> inou.yosys.tolg files:lgdb/parse/chunk_boom.system.TestHarness.BoomConfig.orig.v/FetchTargetQueue.v

lgraph.open name:FetchTargetQueue |> inou.yosys.fromlg

[renau]

rams work now (with the exception of mixing async and sync ports in the same ram)