midnighter95's Stars
amix/vimrc
The ultimate Vim configuration (vimrc)
FelisCatus/SwitchyOmega
Manage and switch between multiple proxies quickly & easily.
tpope/vim-pathogen
pathogen.vim: manage your runtimepath
OpenXiangShan/XiangShan
Open-source high-performance RISC-V processor
riscv-collab/riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
EndlessCheng/mahjong-helper
日本麻将助手:牌效+防守+记牌(支持雀魂、天凤)
nix-community/nix-direnv
A fast, persistent use_nix/use_flake implementation for direnv [maintainer=@Mic92 / @bbenne10]
ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
OSCPU/NutShell
RISC-V SoC designed by students in UCAS
riscv-software-src/riscv-tests
ucb-bar/chisel-tutorial
chisel tutorial exercises and answers
nturley/netlistsvg
draws an SVG schematic from a JSON netlist
bminor/musl
Unofficial mirror of etalabs musl repository. Updated daily.
ucb-bar/berkeley-softfloat-3
SoftFloat release 3
sifive/sifive-blocks
Common RTL blocks used in SiFive's projects
chipsalliance/t1
OpenXiangShan/difftest
Modern co-simulation framework for RISC-V CPUs
SI-RISCV/hbird-e-sdk
Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/
poweihuang17/Documentation_Spike
Documentation for RISC-V Spike
KyleBing/sslist
优化访问速度的小型 gfw (Great Fire Wall) 规则列表 gfwlist
sycuricon/starship
Run rocket-chip on FPGA
ehw-fit/ariths-gen
Generator of arithmetic circuits (multipliers, adders) and approximate circuits
OpenRigil/openrigil-rtl
Open-source RISC-V cryptographic hardware token, RTL repo
ee-uet/UETRV_ESoC
chipsalliance/rocket
The working draft to split rocket core out from rocket chip
sequencer/rocket
A modern version of Rocket Core.
edwardcwang/chisel-multiclock-demo
Chisel Multiclock Demos
riscv-rust/fu740-hal
yqszxx/unmatched-bare
OpenRigil/openrigil-firmware
Open-source RISC-V cryptographic hardware token, firmware repo