milestone12

milestone12's Stars

• torvalds/linux

  Linux kernel source tree

  Language:C178k7.9k053.2k

• ankitects/anki

  Anki's shared backend and web components, and the Qt frontend

  Language:Rust18.3k3449252.1k

• zephyrproject-rtos/zephyr

  Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

  Language:C10.5k40522.3k6.4k

• chipsalliance/chisel

  Chisel: A Modern Hardware Design Language

  Language:Scala3.9k1501k588

• riscv/riscv-isa-manual

  RISC-V Instruction Set Manual

  Language:TeX3.6k206849613

• adafruit/Adafruit-GFX-Library

  Adafruit GFX graphics core Arduino library, this is the 'core' class that all our other graphics libraries derive from

  Language:C2.4k1592341.5k

• ghdl/ghdl

  VHDL 2008/93/87 simulator

  Language:VHDL2.3k1002.2k358

• cocotb/cocotb

  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  Language:Python1.7k1071.9k501

• SpinalHDL/SpinalHDL

  Scala based HDL

  Language:Scala1.6k80721313

• myhdl/myhdl

  The MyHDL development repository

  Language:Python1k79204247

• VUnit/vunit

  VUnit is a unit testing framework for VHDL/SystemVerilog

  Language:VHDL72252602258

• opieters/business-card

  A business card in LaTeX.

  Language:TeX68225475

• veeresht/CommPy

  Digital Communication with Python

  Language:Python5463566178

• VLSI-EDA/PoC

  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

  Language:VHDL539585493

• Digilent/vivado-boards

  Language:Tcl3814431211

• UVVM/UVVM

  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

  Language:VHDL3575418990

• skordal/potato

  A simple RISC-V processor for use in FPGA designs.

  Language:VHDL256242541

• OSVVM/OSVVM

  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

  Language:VHDL221276657

• d-koppenhagen/latex-rechnung

  Eine LaTeX-Rechnungsvorlage.

  Language:TeX1448747

• Vladilit/fpga-multi-effect

  FPGA-based Multi-Effects system for the electric guitar

  Language:VHDL1244127

• JonasNorling/guitarboard

  Cortex-M4 audio DSP board

  Language:C8710011

• optimsoc/optimsoc

  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores

  Language:C791810622

• tmeissner/psl_with_ghdl

  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

  Language:VHDL621142

• shadicode/Arduino_OLED_UI

  Arduino Menu/UI using OLED & Rotary Encoder

  Language:Arduino29229

• chgrl/LaTeX-Rechnung

  Eine LaTeX-Rechnungsvorlage

  Language:TeX244111

• Phaiax/zybocase

  Case for ZYBO Zynq™-7000 Development Board

  Language:OpenSCAD320

• blik-GmbH/zephyr

  Primary GIT Repository for the Zephyr Project

  Language:C1