Project Digital Design II
- Clone this repository
- Open ModelSim and compile all of the .v files
- In ModelSim, click at the riscv_soc_tb and simulate it
- Design is loaded successfully when the transcript shows something like this
- In transcript, type run 250, in order to simulate with 12 clock cycle, and see how values of registers and data_mem changes overtime.
- You can add wave of riscv_soc_tb/rv32/id in order to see the changes of control signals
- Use Vivado
- Take riscv.v as the top-level module for synthesis.
- Note: Leave out inst_mem.v, data_mem,v, riscv_test.v, rischv_test_soc.v and other .txt files