msurzur

msurzur's Stars

• VUnit/vunit

  VUnit is a unit testing framework for VHDL/SystemVerilog

  Language:VHDL727262

• ghdl/ghdl

  VHDL 2008/93/87 simulator

  Language:VHDL2.4k361

• oxyum/sigrok

  The sigrok project aims at creating a portable, cross-platform, Free/Libre/Open-Source logic analyzer software that supports various logic analyzer hardware products.

  Language:C205

• analogdevicesinc/m2k-fw

  M2k firmware for the ADALM-2000 Active Learning Module

  Language:Shell5428

• MParygin/v.scope80

  Simple FPGA dual channel oscilloscope (Spartan3, Verilog, Picoblaze)

  Language:Verilog61

• emulasion/fpga_scope

  FPGA-based digital oscilloscope. This design specifically targets the Spartan 3AN starter kit.

  Language:Verilog53

• maikmerten/riscv-tomthumb

  A small RISC-V RV32I core written in VHDL, intended as testbed for my personal VHDL learning

  Language:VHDL326

• PUTvision/FPGA-FAST

  FPGA FAST image feature detector implementation in VHDL

  Language:VHDL3615

• nimazad/Ethernet-communication-VHDL

  FPGA implementation of Real-time Ethernet communication using RMII Interface

  Language:Verilog137

• ress/VHDL-Pong

  A Pong game written in VHDL using a Xilinx Spartan 3 board. VGA + PS/2 Keyboard + Sound support.

  Language:VHDL208

• MohammedRashad/FPGA-Speech-Recognition

  Expiremental Speech Recognition System using VHDL & MATLAB.

  Language:VHDL4317

• martinjthompson/libv

  Useful set of library functions for VHDL

  Language:VHDL4714

• jeremiah-c-leary/vhdl-style-guide

  Style guide enforcement for VHDL

  Language:Python18938

• g2384/VHDLFormatter

  VHDL formatter web online written in typescript

  Language:TypeScript5220

• inforichland/freezing-spice

  A pipelined RISCV implementation in VHDL

  Language:VHDL9511

• ossu/computer-science

  🎓 Path to a free self-taught education in Computer Science!

  171k21.6k