nahubap

nahubap's Stars

• kmkalpana2001/DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING

  203

• ananthchellappa/excel

  Personal macro workbook and other helpful stuff

  Language:VBA21

• ananthchellappa/SKILL

  Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.

  Language:Shell324

• ananthchellappa/python

  WIP collection of useful python scripts

  Language:Python1

• ananthchellappa/perl

  WIP collection of useful utilities.

  Language:Perl2

• IHP-GmbH/IHP-Open-PDK

  130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design

  Language:HTML32748

• Satvik3799/Physical-design-with-OpenLANE-using-Sky130-PDK

  This is the repository for the workshop conducted by Mr. Krunal Ghosh from VSD.

  Language:Tcl51

• vinta/awesome-python

  An opinionated list of awesome Python frameworks, libraries, software and resources.

  Language:Python212k24.6k

• AnilSarode/deepLearningBook-Notes

  Notes on the Deep Learning book from Ian Goodfellow, Yoshua Bengio and Aaron Courville (2016)

  1

• mattvenn/awesome-opensource-asic-resources

  27036

• amrrs/build_tools_to_automate_python

  Language:Jupyter Notebook134128

• vsdip/rvmyth_avsddac_interface

  Language:Verilog146

• saurabh618/All-Python-codes-of-ZTM-course-by-Andrei-Neagoie

  Language:Jupyter Notebook1.1k660

• aneagoie/ztm-python-cheat-sheet

  2.4k1.3k

• praharshapm/vsdmixedsignalflow

  This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also discusses the steps to modify the current IP layouts inorder to ensure its acceptance by the EDA tools.

  Language:Verilog4117

• shivanishah269/risc-v-core

  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

  Language:Verilog6741

• google/skywater-pdk

  Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

  Language:Python2.9k377

• stevehoover/warp-v

  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

  Language:TL-Verilog22556