nitheeshkm

nitheeshkm's Stars

• airhdl/spi-to-axi-bridge

  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

  Language:VHDL3610

• AngeloJacobo/UberDDR3

  Opensource DDR3 Controller

  Language:Verilog14719

• ATaylorCEngFIET/cmod_s7_reddit

  Language:Tcl1

• OpenBroadcastSystems/ptpmeasure

  PTP/ST-2110/ST-2022-6 real-time measurement tool

  Language:C272

• CESNET/ofm

  Open FPGA Modules

  Language:VHDL228

• CESNET/ndk-app-minimal

  Minimal Application based on Network Development Kit (NDK) for FPGA cards

  Language:VHDL244

• massgravel/Microsoft-Activation-Scripts

  A Windows and Office activator using HWID / Ohook / KMS38 / Online KMS activation methods, with a focus on open-source code and fewer antivirus detections.

  Language:Batchfile87.4k8.5k

• OpenInterpreter/open-interpreter

  A natural language interface for computers

  Language:Python51k4.4k

• Digital-EDA/Digital-IDE

  All in one vscode plugin for HDL development

  Language:Verilog3259

• accelr-net/udma_uart_vip

  VIP and simulation scripts for PULP's UDMA UART module

  Language:SystemVerilog71

• hypernyan/eth_vlg

  Language:SystemVerilog4616

• cwfletcher/buffets

  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.

  Language:Verilog6118

• TheBeastLT/torrentio-scraper

  Language:JavaScript33456

• fpgasystems/Vitis_with_100Gbps_TCP-IP

  100 Gbps TCP/IP stack for Vitis shells

  Language:C++17371

• freecores/ha1588

  Hardware Assisted IEEE 1588 IP Core

  Language:Verilog2212

• intel/rohd-hcl

  A hardware component library developed with ROHD.

  Language:Dart7517

• sylefeb/Silice

  Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

  Language:C++1.3k78

• alexforencich/verilog-pcie

  Verilog PCI express components

  Language:Verilog1k274

• alexforencich/verilog-i2c

  Verilog I2C interface for FPGA implementation

  Language:Verilog498164

• alexforencich/verilog-axis

  Verilog AXI stream components for FPGA implementation

  Language:Python694216

• alexforencich/verilog-axi

  Verilog AXI components for FPGA implementation

  Language:Verilog1.4k421

• sach/System-Verilog-Packet-Library

  System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers

  Language:SystemVerilog6423

• WangXuan95/FPGA-USB-Device

  An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。

  Language:Verilog52787

• krzemienski/awesome-video

  A curated list of awesome streaming video tools, frameworks, libraries, and learning resources.

  Language:HTML1.5k164

• SystemRDL/PeakRDL

  Control and status register code generator toolchain

  Language:Python7916

• jakkra/ZSWatch

  ZSWatch - the Open Source Zephyr™ based Smartwatch, including both HW and FW.

  Language:C2.2k182

• srsran/srsRAN_Project

  Open source O-RAN 5G CU/DU solution from Software Radio Systems (SRS) https://docs.srsran.com/projects/project

  Language:C++436142

• Essenceia/ethernet-physical-layer

  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.

  Language:Tcl125

• open5gs/open5gs

  Open5GS is a C-language Open Source implementation for 5G Core and EPC, i.e. the core network of LTE/NR network (Release-17)

  Language:C1.7k717

• omec-project/upf

  4G/5G Mobile Core User Plane

  Language:Go169104