nndurj's Stars
golang/go
The Go programming language
nim-lang/Nim
Nim is a statically typed compiled systems programming language. It combines successful concepts from mature languages like Python, Ada and Modula. Its design focuses on efficiency, expressiveness, and elegance (in that order of priority).
nvim-telescope/telescope.nvim
Find, Filter, Preview, Pick. All lua, all the time.
PKU-YuanGroup/Open-Sora-Plan
This project aim to reproduce Sora (Open AI T2V model), we wish the open source community contribute to this project.
nvim-treesitter/nvim-treesitter
Nvim Treesitter configurations and abstraction layer
neovim/nvim-lspconfig
Quickstart configs for Nvim LSP
windwp/nvim-autopairs
autopairs for neovim written in lua
folke/todo-comments.nvim
✅ Highlight, list and search todo comments in your projects
nvim-lua/plenary.nvim
plenary: full; complete; entire; absolute; unqualified. All the lua functions I don't want to write twice.
adrienverge/openfortivpn
Client for PPP+TLS VPN tunnel services
norcalli/nvim-colorizer.lua
The fastest Neovim colorizer.
SpinalHDL/SpinalHDL
Scala based HDL
hrsh7th/cmp-nvim-lsp
nvim-cmp source for neovim builtin LSP client
famiu/feline.nvim
A minimal, stylish and customizable statusline for Neovim written in Lua
B-Lang-org/bsc
Bluespec Compiler (BSC)
chipsalliance/chisel-template
A template project for beginning new Chisel work
alecthomas/pawk
PAWK - A Python line processor (like AWK)
RTimothyEdwards/magic
Magic VLSI Layout Tool
DaehwanKimLab/hisat2
Graph-based alignment (Hierarchical Graph FM index)
vhda/verilog_systemverilog.vim
Verilog/SystemVerilog Syntax and Omni-completion
ucb-bar/chiseltest
The batteries-included testing and formal verification library for Chisel-based RTL designs.
radsz/jacop
Java Constraint Programming solver
yupferris/kaze
An HDL embedded in Rust.
ucsc-vama/essent
high-performance RTL simulator
spyder-ide/spyder-vim
A plugin for Spyder to enable Vim keybindings
tree-sitter/tree-sitter-verilog
SystemVerilog grammar for tree-sitter
dpretet/svut
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
BLu85/AES-GCM-128-192-256-bits
Configurable AES-GCM IP (128, 192, 256 bits)
wookayin/is_mosh
Detect whether the current shell is running under mosh
skovaka/stringtie2
Transcript assembly and quantification for RNA-Seq