Issues
- 5
Systemc error when building NVDLA Test Bench
#368 opened by yanyicheng - 0
Corner related to PPA numbers
#372 opened by RAMMOHAN18 - 0
- 0
Error in building verif_trace_player (after the sysc step, in the simv step)
#370 opened by shariethernet - 0
- 2
systemc header error
#335 opened by ConstantPark - 0
make: *** [/remote/sdg_fpga_ae_00/nikithav/ai_design/nvdla/hw/outdir/nv_full/spec/defs/project.def] Error 127
#367 opened by nikitha-vasanth - 0
verilator build failed
#366 opened by fasih0001 - 0
Nvidia npu v
#365 opened by Nasdaq3016 - 5
VCS_HOME should be set appropriately based on the environment. What does it means?
#342 opened by qaziullah - 0
- 1
rams model clarification
#363 opened by HaogeL - 0
Problem with PReLU
#359 opened by timzhang32 - 1
CNN models for nv_small
#360 opened by mtsanic - 0
Meaning Filehandle GEN1 opened only for input at /usr/share/perl5/IO/Tee.pm line 132.
#361 opened by LuccaRoofthooft - 1
-build ready_for_test
#350 opened by zhuzy106 - 1
How does the data and weight is handled in NVDLA?
#358 opened by mtsanic - 0
PDP doesn't support large images
#356 opened by timzhang32 - 1
Deploying a quantized network on NVDLA
#355 opened by nainag - 0
nvdla hw
#357 opened by timzhang32 - 5
Why sdp has two X module?
#351 opened by FengJungle - 0
Now, we can use nvdla to inference yolox.
#354 opened by LeiWang1999 - 0
[FEATURE REQUEST] DLA support for 3D conv
#353 opened by dmenig - 0
- 0
Why current master branch does not support fp16 feature/weight datatype rtl generate
#347 opened by LeiWang1999 - 2
nv_small tmake building ready_for_test error
#349 opened by shemadolev - 1
Did anyone use this workflow on zynq 7000 ?
#348 opened by LeiWang1999 - 1
Psuedo-dual port RAM
#345 opened by aparna1996 - 6
RTL does not build with Verilator 4.039
#334 opened by jameshanlon - 0
Simulation issues in Vivado
#346 opened by Bliipie - 5
Regarding IP creation for NVDLA using VIvado
#341 opened by nagendra7890 - 0
Does CDMA Write Feature Data into CBUF?
#344 opened by Hassan313 - 3
NV_Small Ubuntu 18.04.3 Compilation Error
#330 opened by Hassan313 - 0
HW Compilation Speed Up
#343 opened by Hassan313 - 0
SDP_LUT feature support for nvdla_small
#340 opened by nainag - 0
Synthesis hierarchical report
#339 opened by ndy2 - 1
Synthesis Questions
#338 opened by ndy2 - 0
A Question For RTL Code : tieoff_fifo_depth in different module has different values. How to understand the values?
#337 opened by Scriabing - 0
How does the CMAC work for image input convolution in the test case of img_51x96x4_1x10x4x32_R8G8B8A8_int8_0? Is it different with direct convolution mode?
#336 opened by qiuweishuai - 0
Verilator error on master branch
#332 opened by Sequner - 0
- 0
NVDLA INT8 Scaling
#331 opened by hashimSharif - 0
- 0
what is Filehandle GEN1 opened only for input at /usr/local/share/perl/5.26.1/IO/Tee.pm line 132.
#328 opened by thehalocline - 1
- 0
NVDLA
#326 opened by ting849560395 - 0
how to enable cdma reg read and write.
#325 opened by arvindhbti - 0
nv_small with FP16/32
#324 opened by franout - 0
IRQ in nv_small
#323 opened by franout - 0