A project to implement and test synchronous and asynchronous FIFO using Questasim software.
- Design made 2 versions using Verilog: Synchronous and Asynchronous. Testbench made in 2 versions: System Verilog and Verilog.
- Developed various test cases to verify empty, full, read error, write error and concurrent reads & writes through testbench.
- Implemented gray counter instead of regular counter for read and write pointers in Asynchronous FIFO to avoid glitch conditions.
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