RISC-V Steel is a free and open 32-bit RISC-V processor core for digital designs. It is developed so that you can take advantage of the free RISC-V ISA in new hardware projects, from small embedded designs to complex systems on a chip.
Check out the Getting Started guide!
Key features
-
RV32I+Zicsr+Machine-level ISA - 3-stage pipeline, in-order execution
- Passes all RISC-V Compatibility Test Framework v2.0 tests
- Production-ready
- Single source file written in human-readable Verilog
- Free and open-source (MIT License)
Documentation
The project has gone through significant changes recently, making the old docs obsolete. New docs will be available soon.
License
Steel Core is distributed under the MIT License.
History
Steel Core was developed for the author's final year college project in 2020. The project goal was to help expand the adoption of the RISC-V architecture by creating a RISC-V core with the basic features to run embedded software that is simple to reuse.
Contact
Rafael Calcada (rafaelcalcada@gmail.com)
Acknowledgements
My friend Francisco Knebel and my advisor Ricardo Reis deserve special thanks for their collaboration in this work.