rafee31

rafee31's Stars

• PrincetonUniversity/AutoSVA

  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

  Language:Python7222

• hellovimo/uvm_testbench_gen

  Novel GUI Based UVM Testbench Template Builder

  Language:Python11544

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog1k252

• Siddhi-95/AHB-to-APB-Bridge-Verification

  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

  Language:SystemVerilog6211

• snbk001/100DaysofRTL

  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore

  Language:SystemVerilog263

• yuravg/uvm_tb_cross_bar

  SystemVerilog UVM testbench example

  Language:SystemVerilog2610

• martinKindall/risc-v-single-cycle

  A Single Cycle Risc-V 32 bit CPU

  Language:SystemVerilog263

• AkeelMedina22/RISC-V-Pipelined-Processor

  A Verilog based 5-stage fully functional pipelined RISC-V Processor code.

  Language:SystemVerilog172

• david-fong/Sudoku-SV

  Goal: Write an even higher performing solution generator

  Language:SystemVerilog61

• iammituraj/LIFO-Stack

  Register-based LIFO aka Stack designed in Verilog/System Verilog.

  Language:SystemVerilog42

• GabbedT/UART-Controller

  UART controller that uses a master-slave architecture to enstablish a communication with the other device during the configuration process. This repository provides RTL code and testbench for the device synthesis and simulation, as well as a simple driver to use it in your system.

  Language:SystemVerilog4

• MasterPlayer/axis_uart_bridge

  FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol

  Language:SystemVerilog4

• Ghonimo/Pre_Silicon-AHB-to_APB-Verification

  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

  Language:SystemVerilog133

• PRADEEPCHANGAL/APB-Protocol-Verification-using-UVM

  APB verification using UVM

  Language:SystemVerilog44

• NickSica/RISC-V-CPU

  A RISC-V CPU built in SystemVerilog for use in the DISCO Lab

  Language:SystemVerilog3

• midimaster21b/spi-bfm

  A quick SPI BFM to assist in SPI device testing and development

  Language:SystemVerilog51

• estufa-cin-ufpe/RISC-V-Pipeline

  32-bit 5-stage pipelined RISC-V processor in SystemVerilog

  Language:SystemVerilog33

• dayzGoBy/I-LOVE-CACHE

  Implementation of one-level cache memory for CPU, written on SystemVerilog

  Language:SystemVerilog2

• sts08015/risc-v-lab

  Extended Version of COSE222 Lab

  Language:SystemVerilog2

• midimaster21b/i2c-bfm

  A simple I2C BFM

  Language:SystemVerilog21

• HarieshAnbalagan/RV32I

  Minimalistic RV32I RISC-V Processor in System Verilog

  Language:SystemVerilog2

• MarcEftimie/FPGA-textbook-solutions

  My solutions to exercises in the "FPGA Prototyping By SystemVerilog Examples" by Pong P. Chu.

  Language:SystemVerilog21

• AbdelrahmanHamdyy/RISC-Pipelined-Processor

  5 stages RISC pipelined processor with multiple instructions implemented in verilog including ALU Operations, Interrupts as a state machine, Jumps and branching instructions, Memory operations and more.. following Harvard architecture.

  2

• iremkalkanli/RISC-V-Processor

  Processor with 11 operation codes based on RISC V

  Language:SystemVerilog21

• N-O-O-B-Coder/State-Machine-based-Controller-For-Traffic-Signal

  This repository provides a Verilog code for a state machine based Traffic Signal Controller

  Language:SystemVerilog1

• knyuchen/fifo_model

  Models for Various FIFO & Buffer

  Language:SystemVerilog1

• tianrenz2/Pipeline-Processor

  Pipeline Processor based on RISC-V, implemented forwarding and hazard detection units

  Language:SystemVerilog2

• pranav-nb/APB_BFM

  This is a bus functional model of Advanced Peripheral Bus.

  Language:SystemVerilog1

• jstlwy/riscv32i

  RISC-V 32-bit Base ISA Implementation

  Language:SystemVerilog1

• MeanPaper/Pipeline-RV32i-Processor

  A Pipelined Implementation of the RV32I Processor

  Language:SystemVerilog1