robindust-ce

robindust-ce's Stars

• rust-lang/rustlings

  :crab: Small exercises to get you used to reading and writing Rust code!

  Language:Rust55.2k34168610.3k

• tock/tock

  A secure embedded operating system for microcontrollers

  Language:Rust5.5k120690705

• enjoy-digital/litex

  Build your hardware, easily!

  Language:C3.1k97835575

• Zer0-bit/gaggiuino

  A Gaggia Classic control project using microcontrollers.

  2k10228285

• corundum/corundum

  Open source FPGA-based NIC and platform for in-network compute

  Language:Verilog1.8k88174426

• olofk/serv

  SERV - The SErial RISC-V CPU

  Language:Verilog1.5k3863193

• VUnit/vunit

  VUnit is a unit testing framework for VHDL/SystemVerilog

  Language:VHDL75551623267

• ErichStyger/mcuoneclipse

  McuOnEclipse Processor Expert components and example projects

  Language:HTML736195411.3k

• Digilent/vivado-library

  Language:C5855959320

• VLSI-EDA/PoC

  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

  Language:VHDL555585594

• open-logic/open-logic

  Open Logic FPGA Standard Library

  Language:VHDL385172733

• ztachip/ztachip

  Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.

  Language:C++237102134

• AngeloJacobo/UberDDR3

  Opensource DDR3 Controller

  Language:Verilog2329937

• gsmecher/minimax

  Minimax: a Compressed-First, Microcoded RISC-V CPU

  Language:Verilog20510613

• jeremiah-c-leary/vhdl-style-guide

  Style guide enforcement for VHDL

  Language:Python1931191841

• hamsternz/Artix-7-HDMI-processing

  Receiving and processing 1080p HDMI audio and video on the Artix 7 FPGA

  Language:VHDL18632861

• kevinpt/vhdl-extras

  Flexible VHDL library

  Language:VHDL18124944

• hdl-modules/hdl-modules

  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

  Language:VHDL1197817

• SystemRDL/PeakRDL

  Control and status register code generator toolchain

  Language:Python108124025

• derhuerst/bvg-rest

  An HTTP API for Berlin & Brandenburg public transport.

  Language:JavaScript885204

• pansygrass/ecc

  Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrated Circuits.

  Language:Verilog412020

• hdl-registers/hdl-registers

  An open-source HDL register code generator fast enough to run in real time.

  Language:Python384335

• YosysHQ/eqy

  Equivalence checking with Yosys

  Language:Python378256

• Xilinx/revCtrl

  Revision Control Labs and Materials

  Language:VHDL231809

• georgeyhere/FPGA-Video-Processing

  Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA

  Language:SystemVerilog21102

• BLangOS/VexRiscV_with_HW-GDB_Server

  VexRiscV system with GDB-Server in Hardware

  Language:VHDL20405

• openformal/sva_basics

  This repository is compilation of basics of System Verilog Assertions in context of formal verification

  Language:SystemVerilog18402

• dpretet/svlogger

  SystemVerilog Logger

  Language:SystemVerilog16111

• codecache-fpga/vunit-vc

  Language:VHDL5301

• vogma/OV7670_ArtyA7

  OV7670 camera controller for FPGA written in VHDL

  Language:VHDL1100