/usb-device

USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface

Primary LanguageVerilogMIT LicenseMIT

[WIP] USB 2.0 Device IP Core using Migen

Directory Structure:

.
├── doc
|
├── firmware
│   └── basic.c
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├── gateware
│   ├── ip_repo
│   │   └── USB_Device_1.0
│   └── usb_ulpi.py
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├── LICENSE
|
├── platform
│   └── zybo
│       └── zybo_usb3300.xdc
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└── README.md

  • firmware/basic.c : Basic C code which tests current capability of the IP Core
  • gateware/ip_repo/USB_Device_1.0 : Vivado packaged IP core
  • platform : Platform specific stuff. Currently only features constraints for Zybo platform

How to use:

  1. Run usb_ulpi.py after se...tting up Migen environment
  2. Copy the generated code usb_ulpi.v to gateware/ip_repo/USB_Device_1.0/src/usb_ulpi.v. Overwrite the existing one.
  3. Create Vivado project with the IP and provided constraints file.
  4. Sample Vivado Block Diagram
  5. After bitstream is generated, create Vivado SDK project with provided basic.c file. Run the program on Zybo.