ip-core
There are 26 repositories under ip-core topic.
jofrfu/tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
WangXuan95/FPGA-MPEG2-encoder
An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器，可实现视频压缩。
Parretto/DisplayPort
DisplayPort IP-core
iDoka/GOST-28147-89
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
rohitk-singh/usb-device
USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface
Goshik92/FpgaCha
Implementation of ChaCha20 for Cyclone V FPGA (DE10-nano) easily connectable to HPS (ARM processor)
rubinsteina13/SV_I2S_RX_CORE
Synthesizable SystemVerilog IP-Core of the I2S Receiver
iDoka/GOST-R34.12-2015
Verilog HDL implementation of the GOST R34.12-2015 — a fresh Russian government standard symmetric key block cipher.
iDoka/ipxact-cli-tools
IP-XACT based CLI-tools
Paebbels/pyIPCMI
A Python-based IP Core Management Infrastructure.
vedranMv/axi_spi_master
IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)
esynr3z/pip-hdl
📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip
iDoka/ipyxact
Python-based IP-XACT parser
magictaler/RGB-LED-PWM-Demo-for-Arty-Z7-20
RGB PWM LED Demo project running on ARTY Z7-20 hardware
rubinsteina13/SV_CLARKE_TRANSFORMATION_CORES
Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation
FlorianFrank/Verilog-UART-Custom-IP
A custom UART IP core. Wrting to bare metal I/O pins independent of the FPGA model.
alexo-git/AIC1106-IPcore
The Altera Avalon bus IP core for TI AIC1106 PCM Codec and Software Driver Example
rubinsteina13/SV_DSM_CORE
Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator
Teddy-van-Jerry/ip-doc
LaTeX Class for IP Core Documentation
sbaldzenka/uart_core
UART IP-core for FPGA.
sigma-logic/common-cores
Common cores for internal use under organization. Mostly oriented on Gowin Arora V family
gvd1248/FPGA
This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and .qsf files for pin assignments
jnonino-crpisetta-icomp/articulos
Artículos escritos en base al Proyecto Final de la carrera Ingeniería en Computación FCEFyN UNC
jnonino-crpisetta-icomp/implementacion
Código Verilog y C realizado para la tesis para la Carrera en Ingeniería en Computación FCEFyN UNC
jnonino-crpisetta-icomp/informe
Informe de la Tesis para la Carrera en Ingeniería en Computación FCEFyN UNC
gonzafernan/cese-mys-zynq7
Microarquitecturas y Softcores - CESE - FIUBA