FlorianFrank/Verilog-UART-Custom-IP
A custom UART IP core. Wrting to bare metal I/O pins independent of the FPGA model.
VerilogMIT
Issues
- 0
Feature: Improve clock divider module
#1 opened by FlorianFrank
A custom UART IP core. Wrting to bare metal I/O pins independent of the FPGA model.
VerilogMIT