sgherbst

sgherbst's Stars

• nektos/act

  Run your GitHub Actions locally 🚀

  Language:Go54.3k1651.1k1.4k

• colmap/colmap

  COLMAP - Structure-from-Motion and Multi-View Stereo

  Language:C++7.5k1732k1.5k

• mit-pdos/xv6-riscv

  Xv6 for RISC-V

  Language:C7k95962.6k

• YosysHQ/picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  Language:Verilog3.1k167176748

• verilator/verilator

  Verilator open-source SystemVerilog simulator and lint system

  Language:C++2.5k703.5k589

• aolofsson/awesome-opensource-hardware

  List of awesome open source hardware tools, generators, and reusable designs

  Language:Python1.9k6915170

• cocotb/cocotb

  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  Language:Python1.8k1091.9k505

• The-OpenROAD-Project/OpenROAD

  OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

  Language:Verilog1.5k521.3k533

• alexforencich/verilog-axi

  Verilog AXI components for FPGA implementation

  Language:Verilog1.4k5271438

• K3D-tools/K3D-jupyter

  K3D lets you create 3D plots backed by WebGL with high-level API (surfaces, isosurfaces, voxels, mesh, cloud points, vtk objects, volume renderer, colormaps, etc). The primary aim of K3D-jupyter is to be easy for use as stand alone package like matplotlib, but also to allow interoperation with existing libraries as VTK.

  Language:Python94125310123

• rigtorp/SPSCQueue

  A bounded single-producer single-consumer wait-free and lock-free queue written in C++11

  Language:C++8953020127

• firesim/firesim

  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

  Language:Scala86852429229

• siliconcompiler/siliconcompiler

  Modular hardware build system

  Language:Python8442531984

• aolofsson/awesome-semiconductor-startups

  List of awesome semiconductor startups

  Language:Python440276870

• tensil-ai/tensil

  Open source machine learning accelerators

  Language:Scala35592829

• zeroasiccorp/switchboard

  Communication framework for RTL simulation and emulation.

  Language:Python25575620

• zeroasiccorp/logik

  A configurable RTL to bitstream FPGA toolchain

  Language:Python253717

• zeroasiccorp/umi

  Universal Memory Interface (UMI)

  Language:Verilog1369259

• kost/tty2web

  Share your terminal as a web application in bind/reverse mode

  Language:Go11410722

• siliconcompiler/zerosoc

  Demo SoC for SiliconCompiler.

  Language:SystemVerilog525178

• pulp-platform/morty

  A SystemVerilog source file pickler.

  Language:Rust495205

• Nic30/pyDigitalWaveTools

  Python library for operations with VCD and other digital wave files

  Language:Python476116

• nmoroze/tclint

  EDA-centric utility for linting and analyzing Tcl code.

  Language:Python292291

• siliconcompiler/lambdapdk

  Library of open source Process Design Kits (PDKs)

  Language:SourcePawn27634

• siliconcompiler/lambdalib

  Hardware abstraction library

  Language:Verilog23451

• zeroasiccorp/ebrick-demo

  Demo: how to create a custom EBRICK

  Language:SystemVerilog14400

• zeroasiccorp/zaui

  Generate a website from markdown with a minimum of fuss.

  Language:Svelte9650

• ClandininLab/stimpack

  Precise and flexible generation of stimuli for neuroscience experiments.

  Language:Python7872

• gitkitjs/gitkitjs

  SvelteKit powered static site generator

  Language:Svelte3200

• petersand/simple-base-lib

  Language:C++25