shanyinshuiyue's Stars
rust-embedded/heapless
Heapless, `static` friendly data structures
WKyleGilbertson/rfefifo
Application to stream Radio Front End data to Linux FIFO
fastos/fastsocket
Fastsocket is a highly scalable socket and its underlying networking implementation of Linux kernel. With the straight linear scalability, Fastsocket can provide extremely good performance in multicore machines. In addition, it is very easy to use and maintain. As a result, it has been deployed in the production environment of SINA.
Jamalianpour/EasyFileTransfer
An easy way to transfer file with any size on network with tcp protocol.
edwinkrisnha/SimpleFileTransfer
Simple file transfer VB.NET over TCP
sopynq/huffman-encoding-core
Huffman encoding core (Vivado HLS Project)
A-T-Kristensen/patmos_HLS
Hardware Accelerators (HwAs) constructed in Vivado HLS
regymm/mit_sd_controller_improved
Improved version of http://web.mit.edu/6.111/volume2/www/f2018/tools/sd_controller.v
tomverbeure/intel_jtag_primitive_blog
How to use the Intel JTAG primitive without using virtual JTAG
Hanley-Yao/Zynq7010_eink_controller
这是一个基于Zynq7010的Eink控制器 在ED097TC2上高质量显示帧数高达10FPS
UoB-HPC/PortableFP128
Shim header to provide portable access to IEEE 128b floats in C.
freecores/fast_log
Logarithm function, base-2, single-cycle
sifferman/find_first_set
Find first set operation in Verilog-2001 with logarithmic complexity.
Reconfigurable-Computing/HLStoFPGA
Hilx/SysAlloc-VHDL
VHDL development of the RAM-based Buddy Allocator
skywind3000/preserve-iso
绝版软件保护工程
aignacio/skid_buffer
INTI-CMNB-FPGA/fpga_examples
This project is about FPGA hard blocks and board features. Examples ready to use and verified in hardware.
azraelrabbit/unboxed
Unpacker tool for the BoxedApp application visualization wrapper
diversenok/TokenUniverse
An advanced tool for working with access tokens and Windows security policy.
pyscripter/python4delphi
Free components that wrap up Python into Delphi and Lazarus (FPC)
mnmhdanas/Automatic-washing-machine
This project proposes to demonstrate the capabilities and scope of Verilog HDL by implementing the control system of an automatic washing machine. The above mentioned objective by implementing the Control System of an automatic washing using the Finite State Machine model. The washing machine control system generates all the control signals required for the operation of washing machine and is designed using Verilog HDL.
Gowtham1729/Image-Processing
Image Processing Toolbox in Verilog using Basys3 FPGA
qqwert0/swRDMA
stbrumme/hash-library
Portable C++ hashing library
CMU-SAFARI/DRAM-Bender
DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM2 chips and DDR4 modules of different form factors. Six prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf
afkhawaja/amorphos
AmorphOS open source FPGA operating system project
Cyan4973/Writing_Safer_C_code
Collection of articles on good practices and tools to improve C code quality
kactus2/kactus2dev
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
SanjayRai/VCU1525_HLS_acceleration_framework_split_xDMA
VCU1525_HLS_acceleration_framework_split_xDMA