simoneruffini/MELA
A Modestly Exhaustive dLx Architecture - RISC microprocessor - VHDL implementation - DLX ISA
VerilogGPL-2.0
Issues
- 0
Add arithmetic shifts
#1 opened by bonnee - 2
Implement Register Entity
#8 opened by simoneruffini - 0
Add sge,sle,sne ALU instructions
#2 opened by simoneruffini - 0
Add p4 adder to ALU
#3 opened by simoneruffini - 0
Implement the Instruction Memory entity
#6 opened by simoneruffini - 0
Implement Data Memory
#7 opened by simoneruffini - 1
- 1
Add `r0` behaviour to RF
#5 opened by simoneruffini