sree-chenna03

sree-chenna03's Stars

• mec391/HFT

  Implementation of various DSP/ML/Control algorithms in FPGAs for High Frequency Financial Trading applications

  Language:Python36

• DRubioG/DSP48E2_clone

  This is a replica for the xilinx DSP48E2 in VHDL

  Language:VHDL1

• guido57/EBAZ4205_SDR_HDMI_PS2

  Radio Spectrum Viewer and Software Defined Radio in a cheap FPGA board

  Language:VHDL111

• Gordonei/MyHDL-based-FPGA-DSP-Toolflow

  A library for generating Software Defined Radio-intended DSP code for FPGAs that makes use of the MyHDL (www.myhdl.org) Python library. Targeted at the Rhino Project (see URL).

  Language:Python243

• mingyuanZang/4-port-Gigabit-Ethernet-Switch

  Project in course “FPGA Design for Communication Systems”

  Language:VHDL167

• Dentaku1992/AudioSpectrumAnalyzerInVHDL

  An audio spectrum analyzer written in VHDL to work on a Xilinx Zync7000 ZedBoard

  Language:VHDL91

• splAcharya/DigitalOscilloscope_Zynq7000Soc

  A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.

  184

• adisarip/zpano

  Implementing Image stitching (panorama algorithm) on zedboard FPGA - using Vivado HLS

  Language:C++55

• delhatch/Zedboard_Mandel

  Mandelbrot generator on the Zedboard. The image is output on the VGA port. Pure Verilog RTL, no ARM core.

  Language:VHDL83

• ilaydayaman/CNN_for_SLR

  A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.

  Language:Verilog8930

• ADG4050/FIR-Filter-Hardware-Implementation-PYNQ

  FIR Filter Implementation on PYNQ FPGA Board for Audio Restoration by removing noises.

  Language:Jupyter Notebook1

• ADG4050/Image-Edge-Detection-PYNQ

  Image Edge Detection Sobel Filter Hardware Implementation on PYNQ FPGA Board

  Language:Jupyter Notebook5

• asantoma/pynq-mlp

  3-layer perceptron implemented on a PYNQ-Z1 FPGA board

  Language:Jupyter Notebook2

• neasotho/SystolicArray_FPGA

  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board

  Language:Tcl113

• XAli-SHX/FPGA-Implementation-of-Image-Processing-for-MNIST-Dataset-Based-on-CNN-Algorithm

  FPGA Implementation of Image Processing for MNIST Dataset Based on Convolutional Neural Network Algorithm (CNN)

  Language:VHDL10

• HWAC-DL/hwac_object_tracker

  FPGA accelerated TinyYOLO v2 object detection neural network

  Language:HTML6718

• clkwrkunvrs/FPGA

  This is a combination of verilog and vhdl files from self-taught projects made during my time working in a cyber research lab in Auburn and also projects from coursework in Digital System Design ELEC 4200. The projects were made using an Embedded Micro mojo FPGA, a Zynq 7 zedboard, or a Digitlent Nexys 4 development board.

  Language:Verilog2

• Shrutisinha22/VOTING-MACHINE-USING-ZEDBOARD

  Designed a Simple Voting Machine using FPGAs with Verilog HDL and Vivado ON ZEDBOARD

  Language:Verilog2

• JeffreySamuel/canny_edge_detection_in_FPGA

  In this project, Canny edge detection, one of the efficient edge detection algorithms is implemented on a Zedboard FPGA using verilog. The input image is stored on a PC and fed to the FPGA. The output processed image is displayed on a VGA monitor.

  Language:C11

• nikkatsa7/SpaceInvadersFpgaGame

  Verilog implementation of the classic arcade game Space Invaders for the Zedboard FPGA board

  Language:VHDL4314

• EdNutting/PMOD

  Verilog for interfacing to PMOD modules on a Zedboard FPGA

  Language:Verilog2

• Shaf3y99/OFDM_Verilog

  This repo is about implementing OFDM transmitter on FPGA (Zedboard) using Verilog language and Vivado simulator

  Language:Verilog82

• xiangze/CNN_FPGA

  verilog CNN generator for FPGA

  Language:V3422

• lulinchen/cnn_open

  A hardware implementation of CNN, written by Verilog and synthesized on FPGA

  Language:Coq21873

• ultraembedded/core_jpeg

  High throughput JPEG decoder in Verilog for FPGA

  Language:Verilog21942

• ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA

  Verilog Generator of Neural Net Digit Detector for FPGA

  Language:Verilog29287