Rewrite UART (& PLIC) THRE interrupt from "level-triggered" with "edge-triggered"

[takahirox]

Currently riscv-rust implements THRE (transmission holder register empty) interrupt as "level-triggered" interrupt in UART (and PLIC).

But in the UART spec, it doesn't seem to be mentioned whether it should be "level-triggered" or "edge-triggered". And switching trigger mode is undefined.

The latest (Oct 18 2020) xv6-riscv UART driver seems to expect it is "edge-triggered".

It may be good to rewrite our THRE interrupt from "level-triggered" to "edge-triggered" because the latter one would support more many drivers. I speculate drivers would hardly make the use of "level-triggered" behavior which keeps interrupting while the register is empty.