thierryfischer

thierryfischer's Stars

• hide-key/testamatta

  Language:C551

• NetTLP/libtlp

  A library for PCIe Transaction Layer

  Language:C5111

• KastnerRG/riffa

  The RIFFA development repository

  Language:Verilog765313

• enjoy-digital/litepcie

  Small footprint and configurable PCIe core

  Language:Python466116

• alexforencich/verilog-pcie

  Verilog PCI express components

  Language:Verilog1.1k286

• ZipCPU/wb2axip

  Bus bridges and other odds and ends

  Language:Verilog47798

• flobz/psa_car_controller

  Control psa car with connected_car v4 API.

  Language:Python411216

• EVNotify/EVNotify

  EVNotify allows you to monitor your electric vehicle and let you notify when the specified preset state of charge has been achieved.

  Language:Vue20548

• lambdaconcept/usb2sniffer-qt

  Qt-based software for USB2Sniffer

  Language:C++2915

• lambdaconcept/usbsniffer

  Gateware for USB2Sniffer

  Language:Python2412

• ultraembedded/biriscv

  32-bit Superscalar RISC-V CPU

  Language:Verilog845146

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.2k688

• ZipCPU/dpll

  A collection of phase locked loop (PLL) related projects

  Language:Verilog9626

• controlpaths/blog

  Projects published on controlpaths.com and hackster.io

  Language:Jupyter Notebook384

• xjtuecho/EBAZ4205

  A 5$ Xilinx ZYNQ development board.

  627165

• stevenj/GenPinoutSVG

  Generate Pinout Datasheet in SVG format, from a CSV source file of pin defintions

  Language:Python5710

• sparkfun/Graphical_Datasheets

  Code, final versions, and information on the Sparkfun Graphical Datasheets

  Language:Python13118

• yaqwsx/PcbDraw

  Convert your KiCAD board into a nicely looking 2D drawing suitable for pinout diagrams

  Language:Python1.1k90

• pinout-xyz/Pinout.xyz

  Source files for the Raspberry Pi Pinout documentation website.

  Language:HTML695197

• RISCV-on-Microsemi-FPGA/M2GL025-Creative-Board

  Igloo2 M2GL025 Creative Development Board

  Language:Verilog116

• chipsalliance/Cores-VeeR-EH1

  VeeR EH1 core

  Language:SystemVerilog812219

• magro732/OpenRIO

  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.

  Language:VHDL3419

• ludwig-v/psa-nac-firmware-reverse-engineering

  Continental OVIP firmware reverse engineering for PSA/Stellantis cars (Peugeot, Citroen, DS, Opel)

  Language:Shell10725

• f32c/f32c

  A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

  Language:C402104

• diyruz/diyruz_rt

  Single relay with ds18b20 sensor for TI cc2530 and Sonoff Zigbee

  Language:C6125

• Luos-io/luos_engine

  Open-source and real-time orchestrator for cyber-physical-systems, to easily design, test and deploy embedded applications and digital twins.

  Language:C51154

• presslab-us/ZigBee_OpenEVSE

  ZigBee add-on module for OpenEVSE

  Language:C86

• SmartEVSE/smartevse

  Smart EVSE Electric Vehicle Charging Station

  Language:C9555

• hdl-util/hdmi

  Send video/audio over HDMI on an FPGA

  Language:SystemVerilog1.1k112

• tarun27sh/gdb_graphs

  To visualize function call flow for a C/C++ program using gdb and python

  Language:Python9614