tonyalfred
Fresh Graduate from Electronics and Communications Engineering, Cairo University. Interested in Digital Verification Roles.
Pinned Repositories
Computation-Storage-Design-and-Verification-using-Verilog-and-UVM
Build a UVM Environment for an a computation storage module, that does arithmetic operations where memory resides. Concepts like virtual sequencer, reset agents were used.
Synchronous-FIFO-Design-and-Verification-using-Verilog-and-UVM
Build a UVM Environment for an a Synchronous FIFO. Concepts like virtual sequencer, reset agents, assertions were used.
Universal-Asynchronous-Receiver-Transmitter-UART
Implemented UART TX and RX Modules Using Verilog HDL. The RX Module uses the oversampling scheme in order to estimate the middle points of the transmitted bits and retrieve these points accordingly
Memory-Verification-using-UVM
Build a UVM Environment for an parametrized memory module, including uvm testbench architecture components such as; sequencer, driver, monitor, scoreboard and subscriber. design was verified using QuestaSim.
ALU-Verification-using-SystemVerilog
Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was verified using QuestaSim.
TM4C123-Sample-Codes
ARM-TM4C-CCS
This repository contains all my practice codes of TM4C123GXL coded in CCS7. The Texas Instruments Tiva C LaunchPad board TM4C123G is used for the code. The TM4C123GXL Launchpad has the TM4C123GH6PM microcontroller which is based on the ARM Cortex-M4F microcontroller architecture and clocked at 80 MHz (with 100 DMIPS)
32-bit-Single-Cycle-MIPS-Microprocessor
APB-Master-Agent-UVM-VIP
Register-Bank-Modelling-using-SystemVerilog
tonyalfred's Repositories
tonyalfred/APB-Master-Agent-UVM-VIP
tonyalfred/Computation-Storage-Design-and-Verification-using-Verilog-and-UVM
Build a UVM Environment for an a computation storage module, that does arithmetic operations where memory resides. Concepts like virtual sequencer, reset agents were used.
tonyalfred/Synchronous-FIFO-Design-and-Verification-using-Verilog-and-UVM
Build a UVM Environment for an a Synchronous FIFO. Concepts like virtual sequencer, reset agents, assertions were used.
tonyalfred/Universal-Asynchronous-Receiver-Transmitter-UART
Implemented UART TX and RX Modules Using Verilog HDL. The RX Module uses the oversampling scheme in order to estimate the middle points of the transmitted bits and retrieve these points accordingly
tonyalfred/Memory-Verification-using-UVM
Build a UVM Environment for an parametrized memory module, including uvm testbench architecture components such as; sequencer, driver, monitor, scoreboard and subscriber. design was verified using QuestaSim.
tonyalfred/ALU-Verification-using-SystemVerilog
Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was verified using QuestaSim.
tonyalfred/Register-Bank-Modelling-using-SystemVerilog
tonyalfred/32-bit-Single-Cycle-MIPS-Microprocessor
tonyalfred/TM4123C-Template-Files
tonyalfred/TM4C123-Sample-Codes
tonyalfred/ARM-TM4C-CCS
This repository contains all my practice codes of TM4C123GXL coded in CCS7. The Texas Instruments Tiva C LaunchPad board TM4C123G is used for the code. The TM4C123GXL Launchpad has the TM4C123GH6PM microcontroller which is based on the ARM Cortex-M4F microcontroller architecture and clocked at 80 MHz (with 100 DMIPS)