/Synchronous-FIFO-Design-and-Verification-using-Verilog-and-UVM

Build a UVM Environment for an a Synchronous FIFO. Concepts like virtual sequencer, reset agents, assertions were used.

Primary LanguageVerilog

Synchronous-FIFO-Design-and-Verification-using-Verilog-and-UVM

Test-bench Architecture: generic_uvm_arch

How to run project:

  1. Create project on questasim, in the same folder.
  2. Run 'do run/run_uvm.do' from simulator terminal for uvm environment test, or 'do run/run.do' for direct testbench.