axi

taichi-ishitani/tvip-axi

AMBA AXI VIP

rggen/rggen

Code generation tool for control and status registers

ZipCPU/sdspi

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

taichi-ishitani/tnoc

Network on Chip Implementation written in SytemVerilog

lucky-wfw/ARM_AMBA_Design

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

SystemRDL/PeakRDL

Control and status register code generator toolchain

hdl-modules/hdl-modules

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

RSPwFPGAs/opae-xilinx

OPAE porting to Xilinx FPGA devices.

d953i/Custom_Part_Data_Files

Xilinx PCIe to MIG DDR4 example designs and custom part data files

pulp-platform/axi_mem_if

Simple single-port AXI memory interface

esynr3z/axi_vip_demo

Xilinx AXI VIP example of use

hdl-registers/hdl-registers

An open-source HDL register code generator fast enough to run in real time.

hplp/aes_chisel

Implementation of the Advanced Encryption Standard in Chisel

Wissance/QuickSPI

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

pulp-platform/axi_node

AXI X-Bar

mwrnd/innova2_xcku15p_ddr4_bram_gpio

XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA

Yourigh/Rotary-encoder-VHDL-design

VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.

rggen/rggen-sv-rtl

Common SystemVerilog RTL modules for RgGen

kuoyaoming93/sem-ip_pynq

SEM (Soft Error Mitigation) IP adapted for PYNQ-Z2

bselimoglu/SoC-ZedBoard-Zynq-7000-Labs

Hardware and Software Co-design implementations

pothosware/PothosFPGA

Pothos FPGA computational offload and buffer integration support

gednyengs/dma

Open-Source AXI4 DMA Engine in SystemVerilog and Chisel

olagrottvik/bust

Utility for creating and modifying VHDL bus slave modules

plasoc/axiplasma

AXI/MIPS SoC developed in VHDL with FreeRTOS port. Capable of running either preemptively or cooperatively.

vedranMv/axi_spi_master

IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)

aunics/AHB5

AMBA AHB 5.0 VIP in SystemVerilog based on UVM

MicroTCA-Tech-Lab/libudmaio

Userspace I/O library for Xilinx AXI S2MM DMA

abdelazeem201/Arm-Core

This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.

tanerguven/StreamIF

This project is part of my master's thesis. Source code shared for the publication "StreamIF - AXI4 Memory Mapped to AXI4 Stream Interface Library"

jchengX/AXI_DRIVER

mrengineer/Zynq7000_simpleDMA_IRQ_vivado_linux_userspace

Complete project in Vivado 2022.1 + userspace app for petalinux. Loopback AXI simple DMA transfer.

MatthieuMichon/fpga-jtag-axi-demo

Basic JTAG / AXI demonstration on Xilinx's FPGA.

pulp-platform/axi2per

AXI to Peripheral Interconnect

AranelLindi/AXI_SpaceWire_IP

Standalone IP with ARM-AMBA/AXI capable device. Enables sending and receiving data via SpaceWire protocol. Tested on Xilinx FPGA (ZYNQ).

aryan-programmer/axi_gen_and_sum_primes_fpga

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.