Geeks
pulp-platform
/
axi_mem_if
Simple single-port AXI memory interface
Primary Language
SystemVerilog
Other
NOASSERTION
axi_mem_if GitHub
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Readme
2
Issues
36
Stargazers
8
Watchers
Issues
Open issue
Width mismatches
#4 opened
5 years ago
by
olofk
0
Open issue
WLAST is ignored when FSM is in WAIT_WVALID
#2 opened
7 years ago
by
suehtamacv
0