systemverilog-hdl
There are 72 repositories under systemverilog-hdl topic.
openhwgroup/cva6
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
VUnit/vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
nelsoncsc/ISP_UVM
A Framework for Design and Verification of Image Processing Applications using UVM
SystemRDL/PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
pulp-platform/morty
A SystemVerilog source file pickler.
pulp-platform/axi_mem_if
Simple single-port AXI memory interface
nelsoncsc/easyUVM
A simple UVM example with DPI
snbk001/100DaysofRTL
100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore
pulp-platform/uvm-components
Contains commonly used UVM components (agents, environments and tests).
icglue/icglue
A Tcl-Library for scripted HDL generation
NikhilMukraj/spiking-neural-networks-hardware
An FPGA design for simulating biological neurons
ghosh17/DualCoreProcessor
ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor
nelsoncsc/basic_uvmc_oct
A simple UVM testbench using UVM Connect and Octave
ssayin/riscv32-cosim-model
RISC-V processor co-simulation using SystemVerilog HDL and UVM.
BertVerrycken/BERT
Bit-Efficient Replicator Tech for X, Y, Z axis motor control (3D printers)
stineje/ecen4243S25
Spring 2025 ecen4243 Computer Architecture Lab Material
Choaib-ELMADI/getting-started-with-systemverilog
Getting started with SystemVerilog: Hardware Description Language for design and verification.
jiadong5/ECE385_SP23_ZJUI
Final Project third-perspective-shooting video game PokeHead and some other lab codes and design of ECE385 Digital Systems Laboratory
SalomeDevkule7/Neural-Network-Layer-Generator
Application Specific Integrated Circuit(ASIC)
1varuna/fifo_tb_uvm
Self learnt example to write a UVM based TB. (Under construction).
pulp-platform/axi2per
AXI to Peripheral Interconnect
CaglayanDokme/SystemVerilogExercises
This is a repo where I share the System Verilog exercises that I worked on. Contributions and suggestions are welcome
hcyang99/rv32-core
Arbitary superscalar out-of-order RV32I core, with instruction prefetching and write-back no-write-allocate DCache.
nelsoncsc/basic_uvmc
A simple testbench with two refmods using UVM Connect
stineje/dldfall2023
This repository contains information about Digital Logic Design (ecen 3233) laboratory elements for Fall 2023.
xver/icecream_sv
IceCream for SystemVerilog: Never use $display and `uvm_info to debug SystemVerilog again.
yuri-panchul/tt08-adder-with-flow-control
Submission for Tiny Tapeout 8 - Verilog HDL Projects. An adder with a separate flow control for each argument and the result.
alanmimms/kl10
KL10PV (also called "model B") CPU implemented in SystemVerilog for Xilinx FPGA from MP00301_KL10PV_Jun80 PDFs trying to remain faithful to the original while I learn Verilog
himingway/Parallel_Multiplier
A Parallel Multiplier Using SystemVerilog HDL
mateuspinto/simplified-mips-pipeline
A synthesizable simplified MIPS written in System Verilog
prithvi-narayan-bhat/Custom_RISC_Implementation
An attempt at making a customised RISC processor with five pipelined stages and supporting all RISC-V instruction set
snyderth/SCARA_robot
A SCARA topoology robotic arm
SvrAdityaReddy/Inter_Device_Communication_Protocols
Verilog Codes of various Inter Device Communication Protocols