/axi2per

AXI to Peripheral Interconnect

Primary LanguageSystemVerilogOtherNOASSERTION

AXI to Peripheral Bus Converter

Converts an AXI transaction to a transaction supported by some peripherals in the PULP project (like caches, debug unit, etc.). This version supports peripheral data widths of 32 and 64 bit.

AXI data width has to be 64 bit.