gtkwave

yne/vcd

VCD file (Value Change Dump) command line viewer

dpretet/svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

IBM/hdl-tools

Facilitates building open source tools for working with hardware description languages (HDLs)

ghdl/docker

Scripts to build and use docker images including GHDL

tscheipel/HaDes-V

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

albertxie/iverilog-tutorial

Quickstart guide on Icarus Verilog.

JeffDeCola/my-verilog-examples

A place to keep my synthesizable verilog examples.

maazm007/vsdsquadron-mini-internship

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

Elphel/vdt-plugin

mirror of https://git.elphel.com/Elphel/vdt-plugin

machitgarha/parvaj

Easy and fast VHDL simulation tool, integrating GHDL and GTKWave

umarcor/SIEAV

Co-simulation and behavioural verification with VHDL, C/C++ and Python/m

arhamhashmi01/rv32i-pipeline-processor

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

cclienti/wavedisp

Python classes to create agnostic wave files for HDL simulator viewer

TheOneKevin/icarusext

iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.

SinaKarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

agoessling/rules_verilog

Utilities for working with Verilog within Bazel.

bluecmd/fst-example

Example how to use the Fast Signal Trace (FST) format and library

dbhi/containers

Containerized open and free development tools for Dynamic Binary Hardware Injection (DBHI)

five-embeddev/riscv-gtkwave

GTKWave Decoders for RISCV

GLADICOS/UART

This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog

Alfredosavi/tangnano-hello

Sipeed Tang Nano: Fully Opensource Toolchain for FPGA Synthesis, Place & Route, Simulation and Download/Flash.

NAvi349/rtl-sky130-ws

This is a documentation of the work done as part of the 5 - day RTL Design Workshop using Verilog with SKY130 Technology

arjunrajasekharan/16-bit-DADDA-Multiplier

16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; and FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.

Didula98/Building-a-Simple-Processor

Simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL

dominiksalvet/super-riscv

Superscalar dual-issue RISC-V processor

edaa-org/pyEDAA.ToolSetup

graffou/agravic

Simulation platform that enables VHDL-style C++ coding. VCD generation for easy debug. VHDL code generation using C preprocessor. Simple risc-V rv32i SoC example, + Risc-V test suite and gcc bare-metal example. Linux (or WSL) / clang or gcc / risc-v toolchain / quartus required

Vishakha7501/Sky-130-RTL-Design-and-Synthesis-Workshop-using-Verilog

RTL Design and Synthesis Workshop using Verilog with Sky130 Technology

yousinix/vhdl-docker-template

Template for creating VHDL project using docker

arjunrajasekharan/16bit-Sklansky-Adder

16-bit Slansky Adder design using verilog HDL

GLADICOS/SPACEWIRESYSTEMC

This is a test suit spacewire using a model on systemC with a verilog with graphical interface

johannesbonk/vscode-ghdl-interface

A tool to invoke ghdl/gtkwave functions, including error highlighting

shushantkumar/Encryption-Decryption-Model

A completely functional encryption decryption model with specially generated Asymmetric key verification

muhammadtalhasami/RV32I_Single_Cycle

This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.

Pa1mantri/VSD_Hardware_Design

Pre and Post Synthesis Simulation of a Design VSDMemSOC