/16-bit-DADDA-Multiplier

16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; and FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.

Primary LanguageVerilogMIT LicenseMIT

16-bit-DADDA-Multiplier

16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.

Usage

iverilog dadda_tb.v

Output

-Test Bench TestBenchOutput

-GTK Waveform GTKWave